PIC16F913-ISLASHML datasheet(26/330 Pages) MICROCHIP

26 / 330 page

PIC16F913/914/916/917/946

DS41250F-page 24

2.2

Data Memory Organization

The data memory is partitioned into multiple banks

which contain the General Purpose Registers (GPRs)

and the Special Function Registers (SFRs). Bits RP0

and RP1 are bank select bits.

RP1

RP0

→ Bank 0 is selected

→ Bank 1 is selected

→ Bank 2 is selected

→ Bank 3 is selected

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Function Registers. Above the Special Function

Registers are the General Purpose Registers,

implemented as static RAM. All implemented banks

contain Special Function Registers. Some frequently

used Special Function Registers from one bank are

mirrored in another bank for code reduction and

quicker access.

2.2.1

GENERAL PURPOSE REGISTER

FILE

The register file is organized as 256 x 8 bits in the

PIC16F913/914, 352 x 8 bits in the PIC16F916/917 and

336 x 8 bits in the PIC16F946. Each register is accessed

either directly or indirectly through the File Select

INDF and FSR Registers”).

2.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (see Tables 2-1, 2-2,

2-3 and 2-4). These registers are static RAM.

The Special Function Registers can be classified into

two sets: core and peripheral. The Special Function

Registers associated with the “core” are described in

this section. Those related to the operation of the

peripheral features are described in the section of that

peripheral feature.

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