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PIC16F913-I/ML 数据表(PDF) 31 Page - Microchip Technology |
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PIC16F913-I/ML 数据表(HTML) 31 Page - Microchip Technology |
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31 / 330 page  © 2007 Microchip Technology Inc. DS41250F-page 29 PIC16F913/914/916/917/946 TABLE 2-2: PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 41,226 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 33,227 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 40,226 83h STATUS IRP RP1 RP0 TO PD ZDC C 0001 1xxx 32,226 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 41,226 85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 44,227 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 54,227 87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 62,227 88h TRISD(3) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 71,227 89h TRISE TRISE7(2) TRISE6(2) TRISE5(2) TRISE4(2) TRISE3(5) TRISE2(3) TRISE1(3) TRISE0(3) 1111 1111 76,227 8Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 40,226 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 34,226 8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 35,227 8Dh PIE2 OSFIE C2IE C1IE LCDIE —LVDIE — CCP2IE(3) 0000 -0-0 36,227 8Eh PCON — — — SBOREN — —POR BOR ---1 --qq 39,227 8Fh OSCCON — IRCF2 IRCF1 IRCF0 OSTS(4) HTS LTS SCS -110 q000 88,227 90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 92,227 91h ANSEL ANS7(3) ANS6(3) ANS5(3) ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 43,227 92h PR2 Timer2 Period Register 1111 1111 107,227 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 202,227 94h SSPSTAT SMP CKE D/A PS R/W UA BF 0000 0000 194,227 95h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 55,227 96h IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 54,227 97h CMCON1 — — — — — — T1GSS C2SYNC ---- --10 117,227 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 130,227 99h SPBRG SPBRG7 SPBRG6 SPBRG5 SPBRG4 SPBRG3 SPBRG2 SPBRG1 SPBRG0 0000 0000 132,227 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch CMCON0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 116,227 9Dh VRCON VREN —VRR — VR3 VR2 VR1 VR0 0-0- 0000 118,227 9Eh ADRESL A/D Result Register Low Byte xxxx xxxx 182,227 9Fh ADCON1 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- 181,227 Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: PIC16F946 only, forced ‘0’ on PIC16F91X. 3: PIC16F914/917 and PIC16F946 only, forced ‘0’ on PIC16F913/916. 4: The value of the OSTS bit is dependent on the value of the Configuration Word (CONFIG) of the device. See Section 4.2 “Oscillator Control”. 5: Bit is read-only; TRISE3 = 1 always. |
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