PIC16F913-ISLASHML datasheet(100/330 Pages) MICROCHIP

100 / 330 page

PIC16F913/914/916/917/946

DS41250F-page 98

FIGURE 4-9:

FSCM TIMING DIAGRAM

TABLE 4-2:

SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets(1)

CONFIG(2)

CPD

MCLRE

PWRTE

WDTE

FOSC2

FOSC1

FOSC0

—

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

OSCCON

—

IRCF2

IRCF1

IRCF0

OSTS

HTS

LTS

SCS

-110 x000

OSCTUNE

—

TUN4

TUN3

TUN2

TUN1

TUN0

---0 0000

---u uuuu

PIE2

OSFIE

C2IE

C1IE

LCDIE

—

LVDIE

—

CCP2IE

0000 -0-0

PIR2

OSFIF

C2IF

C1IF

LCDIF

—

LVDIF

—

CCP2IF

0000 -0-0

T1CON

T1GINV

TMR1GE T1CKPS1 T1CKPS0 T1OSCEN

T1SYNC

TMR1CS

TMR1ON

0000 0000

Legend:

= unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.

Note

Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

See Configuration Word register (CONFIG) for operation of all register bits.

OSCFIF

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator

Failure

Note:

The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

Test

Clock Monitor Output

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