CS44800 datasheet(13/80 Pages) CIRRUS

13 / 80 page

DS632F1

CS44800

SWITCHING CHARACTERISTICS - DAI INTERFACE

(VD = 2.5 V, VDX = VDP = VLC = 3.3 V, VLS = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLS.)

15. After powering up, the CS44800, RST should be held low until after the power supplies and clocks are set-

tled.

16. See Table 1 on page 26 for suggested MCLK frequencies.

17. Max DAI sample rate is 96 kHz for One Line and TDM modes of operation.

Parameters

Symbol

Min

Max

Units

RST pin Low Pulse Width

(Note 15)

DAI_MCLK Duty Cycle

(Note 16)

DAI_SCLK Duty Cycle

DAI_LRCK Duty Cycle

DAI Sample Rate

(Note 17)

192

kHz

DAI_SDIN Setup Time Before DAI_SCLK Rising Edge

tds

DAI_SDIN Hold Time After DAI_SCLK Rising Edge

tdh

DAI_SCLK High Time

tsckh

DAI_SCLK Low Time

tsckl

DAI_LRCK Setup Time Before DAI_SCLK Rising Edge

tlrcks

DAI_SCLK Rising Edge Before DAI_LRCK Edge

tlrckd

sck h

sc kl

DA I_ S D IN x

lrcks

lrc k d

DA I_ S C L K

DA I_ L RCK

Figure 6. Serial Audio Interface Timing

Figure 7. Serial Audio Interface Timing - TDM Mode

sckh

sckl

DAI_SDIN1

lrcks

lrckd

DAI_SCLK

(input)

DAI_LRCK

(input)

lrcks

MSB

MSB-1

CS44800 数据表(PDF) 13 Page - Cirrus Logic

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