CS44800 datasheet(43/80 Pages) CIRRUS

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DS632F1

CS44800

6. When driving a single-ended (half-bridged) power output stage, set the RAMP[1:0] bits to ‘11’b and

the required ramp speed, to initiate a ramp cycle when the channel is powered on. Set

MIN_PULSE[4:0] to ‘00000’b.

7. Set the PDN bit to ‘0’b to take the CS44800 out of the power-down state.

8. Start all clocks on the DAI interface (DAI_MCLK, DAI_SCLK, DAI_LRCK). This will initiate the SRC to

begin the lock sequence. The SRC lock function can be configured to cause an interrupt condition

when lock has been completed. This will be indicated by an active INT signal.

9. Wait for the SRC to lock.

10. If using the PSR feedback, jump to “Recommended PSR Calibration Sequence” on page 44. When

finished, continue to step 12. If not using PSR feedback, continue to step 12.

11. Set the appropriate GPIO pin, or other control signal, to enable the power output stage.

12. Enable each channel’s PWM modulator by setting the PDN_PWMxx bit to ‘0’b. If full-bridged, go to

step 14. If single-ended (half-bridged), this will initiate a sequence which will slowly increase the DC

voltage, from 0V to Vpower÷2, across the AC coupling capacitor. This will eliminate the instantaneous

charge across the capacitor which would have caused an audible pop from the speaker.

13. Wait for the ramp-up sequence to complete. The ramp-up function can be configured to cause an

interrupt condition when the ramp period has completed. This will be indicated by an active INT signal.

Once the ramp-up sequence has completed, set the RAMP[1:0] bits to ‘01’b

14. For full-bridged power output stage configurations, the ramp-up sequence is not required. Enabling

the power output stage will not cause an audible pop from the speaker.

15. If using the PSR feedback, set the FEEDBACK_EN bit to ‘1’b.

16. Un-mute all active channels.

17. At this point, the CS44800 is ready to accept audio samples and begin playback.

5.1.3

Recommended PSR Calibration Sequence

1. Set the DEC_SHIFT[2:0]/DEC_SCALE[18:0] coefficient (CPSR) to decimal 1.0 (register 35h = 22h,

36h = 00h, 37h = 00h).

2. Set the PSR_RESET bit to ‘1’b.

3. Set the PSR_EN bit to ‘1’b.

4. Set the PSR_EN bit to ‘0’b.

5. Read DEC_OUTD[23:0].

6. See Figure 30 to adjust the DEC_SHIFT[2:0]/DEC_SCALE[18:0] registers.

7. Continue Recommended Power-Up Sequence.

CS44800 数据表(PDF) 43 Page - Cirrus Logic

CS44800 数据表(HTML) 43 Page - Cirrus Logic

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