11

Integrated

Circuit

Systems, Inc.

ICS9LPR501

1118E—08/08/07

2

B0b7

1

B0b6

1

B0b5

CPU

MHz

SRC

MHz

PCI

MHz

REF

MHz

MHz

DOT

MHz

0

0

0

266.66

0

0

1

133.33

0

1

0

200.00

0

1

1

166.66

1

0

0

333.33

1

0

1

100.00

1

1

0

400.00

11

1

1. FS

the Input/Supply/Common Output Parameters Table for correct values.

Also refer to the Test Clarification Table.

2. FS

specifications in the Input/Supply/Common Output Parameters Table for correct values.

Table 1: CPU Frequency Select Table

96.00

Reserved

100.00

33.33

14.318

48.00

Pin 17

Pin 18

Spread

MHz

MHz

%

00

0

0

0

0

0

1

100.00

100.00

0.5% Down Spread

SRCCLK1 from SRC_MAIN

0

0

1

0

100.00

100.00

0.5% Down Spread

Only SRCCLK1 from PLL3

0

0

1

1

100.00

100.00

1% Down Spread

Only SRCCLK1 from PLL3

0

1

0

0

100.00

100.00

1.5% Down Spread

Only SRCCLK1 from PLL3

0

1

0

1

100.00

100.00

2% Down Spread

Only SRCCLK1 from PLL3

0

1

1

0

100.00

100.00

2.5% Down Spread

Only SRCCLK1 from PLL3

01

1

1

N/A

N/A

N/A

N/A

1

0

0

0

24.576

24.576

None

24.576Mhz on SE1 and SE2

1

0

0

1

24.576

98.304

None

24.576Mhz on SE1, 98.304Mhz on SE2

1

0

1

0

98.304

98.304

None

98.304Mhz on SE1 and SE2

1

0

1

1

27.000

27.000

None

27Mhz on SE1 and SE2

1

1

0

0

25.000

25.000

None

25Mhz on SE1 and SE2

11

0

1

27.000

27 SS

-0.5% Down on Pin 18

27Mhz on SE1 and SE2

11

1

0

N/A

N/A

N/A

N/A

11

1

1

N/A

N/A

N/A

N/A

Comment

PLL 3 disabled

B1b1

B1b4

B1b3

B1b2

Table 2: PLL3 Quick Configuration