19

Integrated

Circuit

Systems, Inc.

ICS9LPR501

1118E—08/08/07

Byte 22 CPU M/N Programming

Bit

Pin

Name

Description

Type

01

Default

7

N Div bit 8

PLL 1 M/N Programming

RW

X

6

N Div bit 9

(Intel PLL1 CPU)

RW

X

5M Div Bit 5

RW

X

4M Div Bit 4

RW

X

3M Div Bit 3

RW

X

2M Div Bit 2

RW

X

1M Div Bit 1

RW

X

0M Div Bit 0

RW

X

Byte 23 CPU M/N Programming

Bit

Pin

Name

Description

Type

01

Default

7

N Div bit 7

PLL 1 M/N Programming

RW

X

6

N Div bit 6

(Intel PLL1 CPU)

RW

X

5

N Div bit 5

RW

X

4

N Div bit 4

RW

X

3

N Div bit 3

RW

X

2

N Div bit 2

RW

X

1

N Div bit 1

RW

X

0

N Div Bit 0

RW

X

Byte 24 CPU Divider Programming

Bit

Pin

Name

Description

Type

0

1

Default

7

Reserved

RW

0

6

Reserved

RW

0

5

Reserved

RW

0

4

Reserved

RW

0

3

CPUDiv3

RW

0000:/2

1000:/8

X

2

CPUDiv2

RW

0001:/3

1001:/12

X

1

CPUDiv1

RW

0010:/5

1010:/20

X

0

CPUDiv0

RW

0011:/7

1011:/28

X

Byte 25 SRC and PCI Divider Programming (CK505 PLL1)

Bit

Pin

Name

Description

Type

0

1

Default

7

PCIDiv3

RW

0000:/2

1000:/8

X

6

PCIDiv2

RW

0001:/3

1001:/12

X

5

PCIDiv1

RW

0010:/5

1010:/20

X

4

PCIDiv0

RW

0011:/9

1011:/36

X

3

SRCDiv3

RW

0000:/2

1000:/8

X

2

SRCDiv2

RW

0001:/3

1001:/12

X

1

SRCDiv1

RW

0010:/5

1010:/20

X

0

SRCDiv0

RW

0011:/9

1011:/36

X

CPU Divider Ratio Programming Bits

PCI Divider Ratio Programming Bits for PLL1

SRC Divider Ratio Programming Bits

Reserved

Byte 63 Special Power Management Features (Rev P Silicon and Higher)

Bit

Pin

Name

Description

RW

0

1

Default

7

Internal flags

RW

0

6

RW

0

5

RW

0

4

RW

0

3

RW

0

2

RW

0

1

SATA PLL

Power Management Feature

RW

off

on

0

0

XTAL PD Control

Controls XTAL on/off in legacy PD

RW

off

on

1