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ICS1893CF 数据表(PDF) 74 Page - Integrated Circuit Systems |
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ICS1893CF 数据表(HTML) 74 Page - Integrated Circuit Systems |
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74 / 126 page ![]() ICS1893CF, Rev. F, 03/01/07 Mar. 2007 74 Chapter 7 Management Register Set ICS1893CF Data Sheet - Release Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. Note: An MDIO read of these bits provides a history of the greatest progress achieved by the auto-negotiation process. In addition, the MDIO read latches the present state of the Auto-Negotiation State Machine for a subsequent read. 7.12.4 100Base-TX Receive Signal Lost (bit 17.10) The 100Base-TX Receive Signal Lost bit indicates to an STA whether the ICS1893CF has lost its 100Base-TX Receive Signal. If this bit is set to a logic: • Zero, it indicates the Receive Signal has remained valid since either the last read or reset of this register. • One, it indicates the Receive Signal was lost since either the last read or reset of this register. This bit is a latching high bit. (For more information on latching high and latching low bits, see Section 7.1.4.1, “Latching High Bits” and Section 7.1.4.2, “Latching Low Bits”.) Note: This bit has no definition in 10Base-T mode. 7.12.5 100Base PLL Lock Error (bit 17.9) The Phase-Locked Loop (PLL) Lock Error bit indicates to an STA whether the ICS1893CF has ever experienced a PLL Lock Error. A PLL Lock Error occurs when the PLL fails to lock onto the incoming 100Base data stream. If this bit is set to a logic: • Zero, it indicates that a PLL Lock Error has not occurred since either the last read or reset of this register. • One, it indicates that a PLL Lock Error has occurred since either the last read or reset of this register. This bit is a latching high bit. (For more information on latching high and latching low bits, see Section 7.1.4.1, “Latching High Bits” and Section 7.1.4.2, “Latching Low Bits”.) Note: This bit has no definition in 10Base-T mode. Table 7-19. Auto-Negotiation State Machine (Progress Monitor) Auto-Negotiation State Machine Auto-Negotiation Progress Monitor Auto- Negotiation Complete Bit (Bit 17.4) Auto- Negotiation Monitor Bit 2 (Bit 17.13) Auto- Negotiation Monitor Bit 1 (Bit 17.12) Auto- Negotiation Monitor Bit 0 (Bit 17.11) Idle 0000 Parallel Detected 0001 Parallel Detection Failure 0010 Ability Matched 0011 Acknowledge Match Failure 0100 Acknowledge Matched 0101 Consistency Match Failure 0110 Consistency Matched 0111 Auto-Negotiation Completed Successfully 1000 |
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