SSM2602CPZ-R21 datasheet(23/28 Pages) AD

23 / 28 page

Preliminary Technical Data

SSM2602

Rev. PrB | Page 23 of 28

DIGITAL AUDIO I/F, ADDRESS 0x07

Table 26. Digital Audio I/F Register Bit Map

BCLKINV

LRSWAP

LRP

WL [1:0]

FORMAT [1:0]

Table 27. Descriptions of Digital Audio I/F Register Bits

Bit Name

Description

Settings

BCLKINV

BCLK inversion control

0 = BCLK not inverted (default)

1 = BCLK inverted

Master mode enable

0 = enable slave mode (default)

1 = enable master mode

LRSWAP

Swap DAC data control

0 = output left- and right-channel data as normal

(default)

1 = swap left- and right-channel DAC data in audio

interface

LRP

Polarity control for clocks in right justified, left justified, and

I2S modes

0 = normal DACLRC and ADCLRC (default), or DSP

Submode 1

1 = invert DACLRC and ADCLRC polarity, or DSP

Submode 2

WL [1:0]

Data-word length control

00 = 16 bits

01 = 20 bits

10 = 24 bits (default)

11 = 32 bits

FORMAT [1:0]

Digital audio input format control

00 = right justified

01 = left justified

10 = I2S format (default)

11 = DSP mode

SAMPLING RATE, ADDRESS 0x08

Table 28. Sampling Rate Register Bit Map

CLKODIV2

CLKDIV2

SR [3:0]

BOSR

USB

Table 29. Descriptions of Sampling Rate Register Bits

Bit Name

Description

Settings

CLKODIV2

CLKOUT divider select

0 = CLKOUT is core clock (default)

1 = CLKOUT is core clock divided by 2

CLKDIV2

Core clock divide select

0 = core clock is MCLK (default)

1= core clock is MCLK divided by 2

SR [3:0]

Clock setting condition

See Table 30 and Table 31.

BOSR

Base oversampling rate

USB mode:

0 = 250 fS (default)

1 = 272 fS

Normal mode:

0 = 256 fS (default)

1 = 384 fS

USB

USB mode select

0 = USB mode disable (default)

1 = USB mode enable

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