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SSM2602CPZ-R21 数据表(PDF) 25 Page - Analog Devices

部件名 SSM2602CPZ-R21
功能描述  Low Power Audio Codec
PDF  28 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

SSM2602CPZ-R21 数据表(HTML) 25 Page - Analog Devices

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Preliminary Technical Data
SSM2602
Rev. PrB | Page 25 of 28
Sampling Rate Register Setting
BOSR
SR3
SR2
SR1
SR0
Normal/USB
MCLK (MHz)
ADC Sampling Rate (kHz)
DAC Sampling Rate (kHz)
0
0
1
1
0
1
12
32
32
0
0
1
1
1
1
12
96
96
1
1
1
1
1
1
12
88.2
88.2
ACTIVE, ADDRESS 0x09
Table 32. Active Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
ACTIVE
Table 33. Descriptions of Active Register Bit
Bit Name
Description
Settings
ACTIVE
Digital core activation control
0 = disable digital core (default)
1 = activate digital core
RESET, ADDRESS 0x0F
Table 34. Reset Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
RESET [8:0]
Table 35. Descriptions of Reset Register Bits
Bit Name
Description
Settings
RESET [8:0]
Write to RESET register to set all control registers to default
setting.
0 = reset (default)
ALC CONTROL 1, ADDRESS 0x10
Table 36. ALC Control 1 Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
ALCSEL [1:0]
MAXGAIN [2:0]
ALCL [[3:0]
Table 37. Descriptions of ALC Control 1 Register Bits
Bit Name
Description
Settings
ALCSEL [1:0]
ALC selection
00: ALC disabled (default)
01: ALC enabled, right channel only
10: ALC enabled, left channel only
11: N/A
MAXGAIN [2:0]
PGA maximum gain
000: −12 dB
001: −6 dB
… 6 dB steps up to
111: 30 dB (default)
ALCL [3:0]
ALC target level
0000: −28.5 dBFS
0001: −27 dBFS
…
1011: −12 dBFS (default)
… 1.5 dB steps up to
1111: −6 dBFS



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