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ADPL44002ACPZN2.5-R7 数据表(PDF) 5 Page - Analog Devices

部件名 ADPL44002ACPZN2.5-R7
功能描述  40V, 200mA, Low Noise, CMOS LDO Linear Regulator
PDF  23 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADPL44002ACPZN2.5-R7 数据表(HTML) 5 Page - Analog Devices

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Data Sheet
ADPL44002
analog.com
Rev. 0
5 of 23
(VIN = VOUT +1V or 2.7V, whichever is greater, VOUT = 5V, VEN = VIN, IOUT = 10mA, CIN = COUT = 2.2µF, CSS = OPEN, TA = 25°C
for typical specifications, TJ = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PRECISION EN INPUT
Logic High
ENHIGH
2.7V ≤ VIN ≤ 40V
1.15
1.22
1.30
V
Logic Low
ENLOW
2.7V ≤ VIN ≤ 40V
1.06
1.12
1.18
V
Logic Hysteresis
ENHYS
2.7V ≤ VIN ≤ 40V
100
mV
Leakage Current
IEN-LKG
EN = VIN or GND, 2.7V ≤ VIN
≤ 40V
0.04
1
µA
Delay Time
tEN-DLY
From EN rising from 0V
to VIN to 0.1 × VOUT, 2.7V ≤
VIN ≤ 40V
80
μs
Output Noise
OUTNOISE
10Hz to 100kHz, all
output voltage options
20
µVRMS
Power Supply
Rejection Ratio
PSRR
1MHz, VIN = 7V, VOUT = 5V
40
dB
100kHz, VIN = 7V, VOUT =
5V
58
dB
10kHz, VIN = 7V, VOUT = 5V
78
dB
1
Based on an endpoint calculation using 100μA and 200mA loads. See Figure 6 for typical load regulation
performance for loads less than 1mA.
2
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the
nominal output voltage. Dropout applies only for output voltages above 2.7V.
3
Start-up time is defined as the time between the rising edge of EN to OUT being at 90% of its nominal value.
4
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified
typical value. For example, the current limit for a 5.0V output voltage is defined as the current that causes the
output voltage to drop to 90% of 5.0V or 4.5V.
Table 2. Input and Output Capacitance, Recommended Specifications
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT AND OUTPUT CAPACITANCE
Minimum Capacitance1
CMIN
TA = −40°C to +125°C
1.5
µF
Capacitor Effective
Series Resistance (ESR)
RESR
TA = −40°C to +125°C
0.001
0.3
Ω
1
The minimum input and output capacitance must be greater than 1.5μF over the full range of operating
conditions. The full range of operating conditions in the application must be considered during device selection
to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,
while Y5V and Z5U capacitors are not recommended for use with any LDO.



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