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ADPL44002ACPZN2.5-R7 数据表(PDF) 13 Page - Analog Devices |
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ADPL44002ACPZN2.5-R7 数据表(HTML) 13 Page - Analog Devices |
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13 / 23 page ![]() Data Sheet ADPL44002 analog.com Rev. 0 13 of 23 THEORY OF OPERATION The ADPL44002 is a low quiescent current, LDO linear regulator that operates from 2.7V to 40V and provides up to 200mA of output current. Drawing a low 240μA of quiescent current (typical) at full load makes the ADPL44002 ideal for portable equipment. Typical shutdown current consumption is less than 3μA at room temperature. Optimized for use with small 2.2µF ceramic capacitors, the ADPL44002 provides excellent transient performance. Internally, the ADPL44002 consists of a reference, an error amplifier, and a PMOS pass transistor. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage. The ADPL44002 is available in four fixed output voltage options, ranging from 1.8V to 5.0V. The ADPL44002 architecture allows any fixed output voltage to be set to a higher voltage with an external voltage divider. For example, a fixed 5V output can be set to a 6V output according to the following equation: ������������������������ = 5������ (1 + ������1 ������2 ) (3) where R1 and R2 are the resistors in the output voltage divider shown in Figure 26. To set the output voltage of the adjustable ADPL44002, replace 5V in Equation 3 with 1.2V. Figure 26. Typical Adjustable Output Voltage Application Schematic It is recommended that the R2 value be less than 200kΩ to minimize errors in the output voltage caused by the SENSE/ADJ pin input current. For example, when R1 and R2 each equal 200kΩ and the default output voltage is 1.2V, the adjusted output voltage is 2.4V. The output voltage error introduced by the SENSE/ADJ pin input current is 1mV or 0.04%, assuming a typical SENSE/ADJ pin input current of 10nA at 25°C. The ADPL44002 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. When EN is high, VOUT turns on, and when EN is low, VOUT turns off. For automatic startup, EN can be tied to VIN. VOUT SENSE/ADJ VIN ADPL44002 GND SS CSS 1nF CIN 2.2µF COUT 2.2µF EN OFF ON VIN = 7V VOUT = 6V R1 2kΩ R2 10kΩ |
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