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ADL5961ACCZ-R7 数据表(PDF) 29 Page - Analog Devices

部件名 ADL5961ACCZ-R7
功能描述  9 kHz to 26.5 GHz Integrated Vector Network Analyzer Front End
PDF  34 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADL5961ACCZ-R7 数据表(HTML) 29 Page - Analog Devices

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Data Sheet
ADL5961
APPLICATIONS INFORMATION
analog.com
Rev. 0 | 29 of 34
Table 11. IF −3 dB Bandwidth vs. CIF2 with CIF1 = 0 (Continued)
CIF2
f−3dB (MHz)
14
0.80
15
0.70
Following the filters are differential output amplifiers with individually
programmable gain. The adjustable gain feature is to accommodate
the actual RF drive level in use, and this feature also enables dy-
namic range optimization of both the forward and reverse channels
over a wide range of port terminations. For example, if the bridge
is terminated with an impedance close to 50 Ω, the bridge output
signal level in the reverse (reflected) channel is much lower than
in the forward (incident) channel. To compensate for this difference,
the reverse channel amplifier can be programmed to a higher gain
setting than the forward channel, so both channels use the full input
dynamic range of the ADC connected to the IF outputs. To achieve
optimal measurement accuracy, a calibration procedure must cover
all used gain setting combinations for the forward and reverse
channels.
The gain for the forward and reverse channel can be programmed
through the FGAIN bits in Register 0x23, Bits[6:0], and the RGAIN
bits in Register 0x24, Bits[6:0], respectively, in 6 dB steps, as
shown in Table 12. Note that the bit values also must be increased
in steps of 6 to select the next gain setting (see Figure 20).
Although gain levels beyond 48 dB are supported, these levels are
usually of little practical significance because amplified noise starts
to saturate the IF channels.
Table 12. IF Amplifier Gain vs. FGAIN and RGAIN Settings
FGAIN, RGAIN
IF Gain (dB)
0 to 5
0
6 to 11
6
12 to 17
12
18 to 23
18
24 to 29
24
30 to 35
30
36 to 41
36
42 to 47
42
48 to 53
48
The adjustable output common-mode level, an up to 8 V p-p out-
put-voltage swing and an up to 200 mA current drive capability, pro-
vides enough flexibility to interface with a broad range of suitable
Σ-Δ, successive approximation register (SAR), or pipeline-based
ADCs with sample rates up to several hundred MHz.



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