Data Sheet

ADL5961

SERIAL PERIPHERAL INTERFACE

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Rev. 0 | 31 of 34

Table 13. ADL5961 SPI Register Details (Continued)

Addr

Name

Bits

Bit Name

Description

Reset

Access

be preceded with a new instruction even though the CS line has not been

deasserted by the SPI controller.

6

CSB_STALL

CS Stalling. When SINGLE_INSTRUCTION is enabled and CSB_STALL is

enabled, the CS signal does not reset the SPI state machine when pulled high.

When CSB_STALL is disabled, the SPI state machine always resets when CS

signal is high.

0x0

R/W

5

CONTROLLER_TARGET_RB Controller or Target Device Readback. Setting this bit allows readback of the

SPI controller flip-flop outputs. Clearing this bit provides access to the internal

SPI register outputs.

0x0

R/W

[4:0]

RESERVED

Reserved.

0x0

R

0x02

DEVICE_CONFIG

[7:2]

RESERVED

Reserved.

0x0

R/W

1

SHUTDOWN

Device Shutdown. If shutdown is asserted, the ADL5961 is powered off. Also

see the EN Interface section.

0x0

R/W

0: Normal Operation.

1: Shutdown.

0

RESERVED

Reserved.

0x0

R

0x03

CHIPTYPE

[7:0]

CHIPTYPE

Chip Type, Read Only.

0x1

R

0x20

LO_CONFIG

[7:5]

RESERVED

Reserved.

0x0

R

4

BYPASS

Bypass LO Path. When asserted, the LO chain is configured to have all

multipliers and dividers turned off. IFMODE and LOMODE have no effect. The

LO inputs are connected to the RF mixers by the LO amplifier only.

0x1

R/W

[3:2]

OFMODE

OFMODE. Configures the divider in the offset reference frequency interface.

0x2

R/W

00: ×1 no dividers enabled.

01: Divide by 2 mode.

10: Divide by 4 mode.

11: Dividers off, offset reference signal disconnected.

[1:0]

LOMODE

LOMODE. Configures the LO chain divider and multipliers.

0x1

R/W

00: Divide by 2.

01: Multiply by 1×.

10: Multiply by 2 (2×).

11: Multiply by 4 (4×).

0x21

CT2

[7:5]

RESERVED

Reserved.

0x0

R

[4:0]

CT2

CT2 Filter Setting. Sets the center frequency of the filter in the 2× frequency

multiplier in the LO interface.

0x0

R/W

0x22

CT4

[7:4]

RESERVED

Reserved.

0x0

R

[3:0]

CT4

CT4 Filter Setting. Sets the center frequency of the filter in the 4× frequency

multiplier in the LO interface.

0x0

R/W

0x23

FGAIN

7

RESERVED

Reserved.

0x0

R

[6:0]

FGAIN

Forward Gain. Configures the gain of the IF amplifier in the forward path, to

the IFFP and IFFM output, in 6 dB steps. Decimal register value represents

the gain in dB.

0x0

R/W

0x24

RGAIN

7

RESERVED

Reserved.

0x0

R

[6:0]

RGAIN

Reverse Gain. Configures the gain of the IF amplifier in the reverse path, to

the IFRP and IFRM output, in 6 dB steps. Decimal register value represents

the gain in dB. See Table 12.

0x0

R/W

0x25

CIF2_CIF1

[7:4]

CIF2

Narrow-Band IF Filter Setting. Sets the corner frequency of the narrow

bandwidth IF filter. See Figure 25.

0x0

R/W

[3:0]

CIF1

Wideband IF Filter Setting. Sets the corner frequency of the wide bandwidth IF

filter. See Figure 22.

0x0

R/W