Data Sheet

ADL5961

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 8 of 34

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

AVCC

Analog Positive Power Supply Pin. Bypass by placing 1 nF and 4.7 μF capacitors as closely as possible to the AVCC pin. On power-up,

apply the AVCC voltage before the OVDD voltage. On power-down, remove the OVDD voltage before the AVCC voltage.

2, 4, 18, 20

AGND

Analog Ground Pins. All ground pins are internally connected. Use Pin 2 and Pin 4 as the RF return ground for the RFIN transmission line

(Pin 3). Use Pin 18 and Pin 20 as the RF return ground for the RFOUT transmission line (Pin 19).

3, 19

RFIN, RFOUT

RF Input and Output of the Primary Transmission Line. RFIN and RFOUT have a 50 Ω load characteristic impedance. DC-blocking

capacitors are required to source and load. When using open and short terminations, do not exceed the maximum power dissipation

ratings.

5

CAP

Bypass Capacitor. A 100 nF capacitor is recommended for 100 kHz operation.

6, 7, 15, 16

IFFM, IFFP,

IFRP, IFRM

Differential IF Outputs. Pin 6 and Pin 7 are coupled to the forward power transfer (from RFIN to RFOUT). Pin 15 and Pin 16 are coupled to

the reverse power transfer (from RFOUT to RFIN).

8, 14

OVCC

IF Amplifier Positive Power Supply Pin. Bypass OVCC with a 1 nF and a 4.7 μF capacitor on each pin before connecting to AVCC. Place

the capacitors as closely as possible to OVCC. On power-up, apply the OVCC voltage before the OVDD voltage. On power-down, remove

the OVDD voltage before the OVCC voltage.

9, 10

LOP, LOM

Downconversion Mixer LO Inputs. LOP and LOM are internally terminated with a 100 Ω differential. A differential or single-ended signal

source can drive the LOP and LOM pins. Register 0x20 configures the LO interface. DC-blocking capacitors are recommended for the LO

interface.

11

SYNC

Synchronization Input. This complementary metal-oxide semiconductor (CMOS) input pin stops the dividers in the LO and IF input

interfaces when driven high and initiates synchronization when driven back low. If left floating, an internal 415 kΩ pull-down resistor

disables the SYNC function.

12, 13

OFP, OFM

IF Offset Reference Frequency Inputs. The OFP and OFM pins set the center frequency at the IF outputs when the OFMODE bits

(Bits[3:2]) in Register 0x20 equal 0x0, 0x1, or 0x2. Setting the OFMODE bits to 0x3 disables this input.

17

VCM

IF Output Common-Mode Voltage Control. The VCM pin sets the output common-mode voltage at IFFM, IFFP, IFRP, and IFRM. Floats to

OVCC/2 if left open.

21

TEMP

Temperature Sensing Diode. The TEMP pin connects to the anode of an on-chip junction diode. TEMP can be used to measure the die

temperature by measuring the voltage at this pin, while forcing a known current into the pin.

22

OVDD

SPI Positive Power Supply Pin. Connect the OVDD pin to the power supply of the SPI controller to avoid the need of voltage level

translators in the SPI bus connections. On power-up, apply the AVCC and OVCC voltages before the OVDD voltage. On power-down,

remove the OVDD voltage before the AVCC and OVCC voltages.

23

SDIO

SPI Data Input and Output. If the SDIO pin is floating, an internal 415 kΩ pull-down resistor pulls SDIO to logic low.

24

CS

SPI Chip Select (Active Low). If the CS pin is floating, an internal 415 kΩ pull-up resistor ties the pin to OVDD.

25

SCK

SPI Clock Input. If SCK is left floating, an internal 415 kΩ pull-down resistor pulls SCK to logic low.

26

EN

Chip Enable. A logic high at the EN pin enables the chip. A logic low at the EN pin shuts down the ADL5961. If EN is left floating, an

internal 415 kΩ pull-down resistor disables the ADL5961.

EPAD

Exposed Pad. The exposed pad (EPAD) on the underside of the device is also internally connected to ground and requires good thermal

and electrical connection to the ground of the PCB. Connect all ground pins to a low impedance ground plane together with the EPAD.