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Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).

Fig 18. Read input port register, scenario 2

1

A

S

START condition

R/W

acknowledge

from slave

002aac313

A

acknowledge

from master

SCL

SDA

A

read from port 0

data into port 0

INT

A

1

no acknowledge

from master

P

DATA 10

DATA12

9

8

7

6

5

4

3

2

1

P0x

DATA 00

acknowledge

from master

P1x

P0x

acknowledge

from master

P1x

data into port 1

DATA 00

read from port 1

DATA 11

DATA 01

DATA 02

DATA 03

A5 A4 A3 A2 A1 A0

A6

DATA 10

DATA 03

DATA 12