PCA9673_1

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 01 — 1 February 2007

20 of 33

NXP Semiconductors

PCA9673

[1]

[2]

Each bit must be limited to a maximum of 25 mA and the total package limited to 400 mA due to internal busing limits.

[3]

The value is not tested, but verified on sampling basis.

13. Dynamic characteristics

Table 6.

Dynamic characteristics

Symbol Parameter

Conditions

Standard mode

Fast-mode

Unit

Min

Max

Min

Max

Min

Max

SCL clock frequency

0

100

0

400

0

1000

kHz

bus free time between a

STOP and START condition

4.7

-

1.3

-

0.5

-

µs

hold time (repeated) START

condition

4.0

-

0.6

-

0.26

-

µs

set-up time for a repeated

START condition

4.7

-

0.6

-

0.26

-

µs

set-up time for STOP

condition

4.0

-

0.6

-

0.26

-

µs

data hold time

0

-

0

-

0

-

ns

data valid acknowledge

time[1]

0.3

3.45

0.1

0.9

0.05

0.45

µs

data valid time[2]

300

-

50

-

50

450

ns

data set-up time

250

-

100

-

50

-

ns

LOW period of the SCL clock

4.7

-

1.3

-

0.5

-

µs

HIGH period of the SCL

clock

4.0

-

0.6

-

0.26

-

µs

fall time of both SDA and

SCL signals

[4][5]

-

300

300

-

120

ns

rise time of both SDA and

SCL signals

-

1000

300

-

120

ns

pulse width of spikes that

must be suppressed by the

input filter[6]

-

50

-

50

-

50

ns

data output valid time

-

4

-

4

-

4

µs

data input set-up time

0

-

0

-

0

-

µs

data input hold time

4

-

4

-

4

-

µs

data input valid time

-

4

-

4

-

4

µs

reset delay time

-

4

-

4

-

4

µs

Reset timing (see Figure 27)

reset pulse width

4

-

4

-

4

-

ns

reset recovery time

0

-

0

-

0

-

ns

reset time

100

-

100

-

100

-

ns