PCA9673D datasheet(21/33 Pages) PHILIPS

21 / 33 page

PCA9673_1

Product data sheet

Rev. 01 — 1 February 2007

21 of 33

NXP Semiconductors

PCA9673

Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt and reset

[1]

tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[2]

tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.

[3]

Cb = total capacitance of one bus line in pF.

[4]

A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to

bridge the undeﬁned region SCL’s falling edge.

[5]

The maximum tf for the SDA and SCL bus lines is speciﬁed at 300 ns. The maximum fall time for the SDA output stage tf is speciﬁed at

250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without

exceeding the maximum speciﬁed tf.

[6]

Input ﬁlters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

Rise and fall times refer to VIL and VIH.

Fig 26. I2C-bus timing diagram

SCL

SDA

tHD;STA

tSU;DAT

tHD;DAT

tBUF

tSU;STA

tLOW

tHIGH

tVD;ACK

002aab175

tSU;STO

protocol

START

condition

(S)

bit 7

MSB

(A7)

bit 6

(A6)

bit 0

(R/W)

acknowledge

(A)

STOP

condition

(P)

1/fSCL

tVD;DAT

Fig 27. Reset timing

SDA

SCL

002aac282

trst

50 %

30 %

50 %

trec(rst)

tw(rst)

RESET

P0n, P1n

output off

START

trst

ACK or read cycle

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