AS7C1028

12/5/06; V.1.0

Alliance Memory

P. 2 of 8

®

Functional description

The AS7C1028 is a 5V

high-performance CMOS 1,048,576-bit Static Random-Access Memory (SRAM) device organized

as 262,144 words × 4 bits. It is designed for memory applications requiring fast data access at low voltage, including

operation without sacrificing performance or operating margins.

expansion with multiple-bank memory organizations.

A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is

written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive

I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The

chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write

enable is low, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0±0.5V supply. The AS7C1028 is packaged in

high volume industry standard packages.

Absolute maximum ratings

Note:

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect reliability.

Truth table

Notes:

Parameter

Symbol

Min

Max

Unit

–0.5

+7.0

V

Voltage on any pin relative to GND

–0.5

V

Power dissipation

–1.25

W

Storage temperature (plastic)

–55

+125

–55

+125

DC current into outputs (low)

–50

mA

CE

WE

OE

Data

Mode

H

X

X

High Z

L

H

H

High Z

LH

L

LL

X