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AS7C1028 数据表(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS7C1028 数据表(HTML) 1 Page - Alliance Semiconductor Corporation |
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1 / 8 page ![]() September 2006 Advance Information Copyright © Alliance Memory. All rights reserved. AS7C1028 12/5/06; V.1.0 Alliance Memory P. 1 of 8 5V 256K X 4 CMOS SRAM (Common I/O) ® Features • Industrial (-40o to 85oC) temperature • Organization: 262,144 words × 4 bits • High speed - 12 ns address access time - 6 ns output enable access time • Low power consumption via chip deselect • One chip select plus one Output Enable pin • Bidirectional data inputs and outputs • TTL-compatible • 28-pin JEDEC standard packages - 400 mil SOJ • ESD protection ≥ 2000 volts Logic block diagram A 11 A 10 262,144 x 4 Array (262,144) Input buffer A0 A1 A2 A3 A4 A5 A6 A7 A 12 A 13 A 14 A 15 A 16 I/O0 I/O3 VCC GND OE CE WE Address decoder Control circuit A8 A9 A 17 Pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 VCC A17 A16 A15 A14 A13 A12 A11 NC I/O3 I/O2 I/O1 I/O0 WE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE OE GND 16 15 28 Pin SOJ (400 mil) |
类似零件编号 - AS7C1028 |
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类似说明 - AS7C1028 |
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