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AS7C1028 数据表(PDF) 5 Page - Alliance Semiconductor Corporation |
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AS7C1028 数据表(HTML) 5 Page - Alliance Semiconductor Corporation |
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5 / 8 page ![]() AS7C1028 12/5/06; V.1.0 Alliance Memory P. 5 of 8 ® Write cycle (over the operating range)11 Shaded areas contain advance information. Write waveform 1 (WE controlled)10,11 Write waveform 2 (CE controlled)10,11 Parameter Symbol AS7C1028-12 Unit Notes Min Max Write cycle time tWC 12 – ns Chip enable to write end tCW 10 – ns Address setup to write end tAW 10 – ns Address setup time tAS 0– ns Write pulse width tWP 10 – ns Write recovery time tWR 0– ns Address hold from end of write tAH 0– ns Data valid to write end tDW 7– ns Data hold time tDH 0 – ns 4, 5 Write enable to output in high Z tWZ 0 5 ns 4, 5 Output active from write end tOW 3 – ns 4, 5 tAW tAH tWC Address WE Din Dout tDH tOW tDW tWZ tWP tAS tWR Data valid tAW Address CE WE Din Dout Data valid tCW tWP tDW tDH tAH tWZ tWC tAS tWR |
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