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AS7C3513C 数据表(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS7C3513C 数据表(HTML) 1 Page - Alliance Semiconductor Corporation |
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1 / 9 page ![]() September 2006 Advance Information Copyright © Alliance Memory. All rights reserved. AS7C3513C 3.3 V 32K X 16 CMOS SRAM 9/5/06, v 1.0 Alliance Memory P. 1 of 9 ® Features • Industrial (-40o to 85oC) temperature • Organization: 32,768 words × 16 bits • Center power and ground pins for low noise • High speed - 10 ns address access time - 5 ns output enable access time • Low power consumption via chip deselect • Upper and Lower byte pin • Easy memory expansion with CE, OE inputs • TTL-compatible, three-state I/O • JEDEC standard packaging - 44-pin 400 mil SOJ - 44-pin TSOP 2 • ESD protection ≥ 2000 volts Logic block diagram 32,768 × 16 Array OE CE WE Address decoder A0 A1 A2 A3 A4 A5 A7 VCC GND Control circuit I/O0–I/O7 I/O8–I/O15 UB LB I/O buffer A6 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A7 A8 A9 A10 NC A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A14 A13 A12 44-Pin SOJ (400 mil), TSOP 2 21 22 A11 NC UB LB I/O15 I/O14 2 A3 3 A2 4 A1 1 NC 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 A5 A6 OE A4 Pin arrangement |
类似零件编号 - AS7C3513C |
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类似说明 - AS7C3513C |
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