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A

B

1.62 k

Ω , ±1%

tc(n)

1/f0

0 V

0 V

Period Jitter

0 V

Peak to Peak Jitter

1/f0

PRBS INPUT

OUTPUT

CLOCK

INPUT

IDEAL

OUTPUT

ACTUAL

OUTPUT

0 V

0 V

Cycle to Cycle Jitter

0 V

OUTPUT

R

A

B

SN65MLVD080

SN65MLVD082

SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 7. Maximum Steady State Output Voltage

A.

All input pulses are supplied by an Agilent 8304A Stimulus System with plug-in TBD.

B.

The measurement is made on a TEK TDS6604 running TDSJIT3 application software

C.

Period jitter and cycle-to-cycle jitter are measured using a 100 MHz 50

±1% duty cycle clock input.

D.

Figure 8. Driver Jitter Measurement Waveforms

Figure 9. Receiver Voltage and Current Definitions

9

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