5.5 Electrical Characteristics (continued)

VDD, VDD_A = 3.3 V ± 5 %, -40 °C < TA < 85 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tSKEW

Skew between outputs

(6)

50

ps

JCKx_PCIE

Additive jitter

DB2000QL filter

0.08 ps, rms

Additive jitter for PCIe5

PCIe5.0 filter

0.03 ps, rms

Additive jitter for PCIe4

PLL BW = 2 - 5 MHz; CDR =

10 MHz

Input clock

slew rate ≥

1.8 V/ns

0.08 ps, rms

Additive jitter for PCIe3

Input clock

slew rate ≥

0.6 V/ns

0.15 ps, rms

JCKx_PCIE

Additive jitter for PCIe2

PCIe2 filter

0.2 ps, rms

JCKx_PCIE

Additive jitter for PCIe1

PCIe1 filter

5 ps, rms

JCKx

Additive jitter

fIN = 100 MHz; slew rate ≥ 3 V/ns; 12 kHz to

20 MHz integration bandwidth.

155

fs, rms

SMBUS INTERFACE, SIDE-BAND INTERFACE, OEx#, CKPWRGD_PD#, SBEN

VIH

High-level input voltage

2.0

V

VIL

Low-level input voltage

0.8

IIL

Input leakage current

With internal pull up/pull-down

GND < VIN

< VDD

–30

30

uA

Without internal pull up/pull-

down

–5

5

CIN

Input capacitance

4.5

pF

COUT

Output capacitance

4.5

pF

3-LEVEL DIGITAL INTERFACE (SA_0, SA_1)

VIHT

High-level input voltage

2.4

V

VIMT

Mid level input voltage

1.3

VDD/2

1.8

VILT

Low-level input voltage

0.9

IINT

Input high current

VIN = VDD, VIN = GND

-10

10

uA

ILeak

Input leakage current

With internal pull up/pull-down

GND < VIN

< VDD

–30

30

(1)

Voltage swing includes overshoot.

(2)

Not tested in production. Ensured by design and characterization.

(3)

Measured into DC test load.

(4)

VCROSS is single-ended voltage when CKx_P = CKx_N with respect to system ground. Only valid on rising edge of CKx, when CKx_P

is rising.

(5)

Measured from rising edge of CLK_IN to any CKx output.

(6)

Measured from rising edge of any CKx output to any other CKx output.

5.6 Timing Requirements

VDD, VDD_A = 3.3 V ± 5 %, -40 °C < TA < 85 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise

noted)

MIN

NOM

MAX

UNIT

SMBUS-COMPATIBLE INTERFACE TIMING

fSMB

SMBus operating frequency

10

100

kHz

tBUF

Bus free time between STOP and START

4.7

µs

tHD_STA

START condition hold time

4

tSU_STA

START condition setup time

4.7

tSU_STO

STOP condition setup time

4

tHD_DAT

SMBDAT hold time

300

ns

tSU_DAT

SMBDAT setup time

250

CDCDB2000

SNAS787B – NOVEMBER 2019 – REVISED OCTOBER 2024

www.ti.com

8

Submit Document Feedback

Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: CDCDB2000