7.1.3 OECR3 Register (Address = 2h) [reset = FFh]

OECR3 is shown in Table 7-5.

Return to the Summary Table.

The OECR3 register contains bits that enable or disable individual output clock channels [15:8]

Table 7-5. OECR3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

Output Enable, CK15

R/W

1h

This bit controls the output enable signal for output channel CK15_P/

CK15_N.

0h = Output Disabled

1h = Output Enabled

6

Output Enable, CK14

R/W

1h

This bit controls the output enable signal for output channel CK14_P/

CK14_N.

0h = Output Disabled

1h = Output Enabled

5

Output Enable, CK13

R/W

1h

This bit controls the output enable signal for output channel CK13_P/

CK13_N.

0h = Output Disabled

1h = Output Enabled

4

Output Enable, CK12

R/W

1h

This bit controls the output enable signal for output channel CK12_P/

CK12_N.

0h = Output Disabled

1h = Output Enabled

3

Output Enable, CK11

R/W

1h

This bit controls the output enable signal for output channel CK11_P/

CK11_N.

0h = Output Disabled

1h = Output Enabled

2

Output Enable, CK10

R/W

1h

This bit controls the output enable signal for output channel CK10_P/

CK10_N.

0h = Output Disabled

1h = Output Enabled

1

Output Enable, CK9

R/W

1h

This bit controls the output enable signal for output channel CK9_P/

CK9_N.

0h = Output Disabled

1h = Output Enabled

0

Output Enable, CK8

R/W

1h

This bit controls the output enable signal for output channel CK8_P/

CK8_N.

0h = Output Disabled

1h = Output Enabled

7.1.4 OERDBK Register (Address = 3h) [reset = 0h]

OERDBK is shown in Table 7-6.

Return to the Summary Table.

The OERDBK register contains bits that report the current state of the OE[12:5]# input pins.

Table 7-6. OERDBK Register Field Descriptions

Bit

Field

Type

Reset

Description

7

OE12# State

R

0h

This bit reports the logic level present on the OE12# pin.

6

OE11# State

R

0h

This bit reports the logic level present on the OE11# pin.

5

OE10# State

R

0h

This bit reports the logic level present on the OE10# pin.

4

OE9# State

R

0h

This bit reports the logic level present on the OE9# pin.

CDCDB2000

SNAS787B – NOVEMBER 2019 – REVISED OCTOBER 2024

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