PWRGD

PD#

CKPWRGD_PD#

VDD/VDD_A

Figure 6-1. PWRGD and PD# State Changes

6.4.2 OE[12:5]# and SMBus Output Enables

Each output channel, 0 to 19, can be individually enabled or disabled by SMBus control register bits, called SMB

enable bits. Additionally, each output channel from 12 to 5 has a dedicated, corresponding, OE[12:5]# hardware

pin. The OE[12:5]# pins are asynchronously asserted-low signals that may enable or disable the output.

Refer to Table 6-2 for enabling and disabling outputs through the hardware and software. Note that both the

SMB enable bit must be a ‘1’ and the OEx# pin must be an input low voltage ‘0’ for the output channel to be

active.

Table 6-2 is only valid when the SBEN signal is low (SBEN = 0).

Table 6-2. OE[12:5]# Functionality When SBEN = 0

INPUTS

OE[12:5]# HARDWARE PINS AND SMBus CONTROL REGISTER BITS

PWRGD

PD#

CLKIN

SMBus ENABLE BIT

(byte[2:0])

OE[12:5]#

CK[12:5]

CK[19:13, 4:0]

0

X

X

X

X

LOW

LOW

1

0

X

X

X

Tristate

Tristate

1

1

Running

0

X

0

0

1

1

Running

1

0

Running

Running

1

1

Running

1

1

0

Running

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CDCDB2000

SNAS787B – NOVEMBER 2019 – REVISED OCTOBER 2024

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