VDD, VDD_A = 3.3 V ± 5 %, -40 °C < TA < 85 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise

noted)

MIN

NOM

MAX

UNIT

tTIMEOUT Detect SMBCLK low timeout

25

35

ms

tLOW

SMBCLK low period

4.7

µs

tHIGH

SMBCLK high period

4

50

tLOW_SL

Cumulative clock low extend time

25

ms

tF

SMBCLK/SMBDAT fall time(1)

300

ns

tR

SMBCLK/SMBDAT rise time(2)

1000

SIDE-BAND INTERFACE TIMING

tPERIOD

Clock period

40

ns

tSETUP

Setup time to clock

25

tDSU

Data set up time

10

tDHOLD

Data hold time

5

tDELAY

Delay time

25

tPDLY

Propagation delay

4

10

CLK

periods

tSLEW

Clock slew rate

20% - 80%

0.2

3

V/ns

(1)

TF = (VIHMIN + 0.15) to (VILMAX - 0.15)

(2)

TR = (VILMAX - 0.15) to (VIHMIN + 0.15)

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CDCDB2000

SNAS787B – NOVEMBER 2019 – REVISED OCTOBER 2024

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