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Data Sheet

ADL5511

CIRCUIT DESCRIPTION

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Rev. E | 17 of 26

The ADL5511 employs a proprietary rectification technique to strip

off the carrier of an input signal to reveal the true envelope. In

this first detection stage, the carrier frequency is doubled and an

on-chip two-pole passive low-pass filter accurately preserves the

envelope and filters out the carrier. The poles of this filter, as de-

fined by the on-chip RC filters (0.4 pF, 400 Ω, 0.8 pF, 250 Ω) values

allow some carrier leakthrough for common RF frequencies. This

is to ensure that maximum envelope bandwidth can be maintained.

For more details, see the Basic Connections section.

Figure 48. Block Diagram

The extracted envelope is further processed in two parallel chan-

nels, one computing the rms value of the envelope and the other

transferring the envelope with appropriate scaling to the envelope

output.

ENVELOPE PROPAGATION DELAY

The delay specified in this data sheet is with no external capacitor

at the FLT2 and FLT3 pins. The delay through the ADL5511,

although very small, depends upon a number of factors, notable

of which are internal filter component values and op amp compen-

sation capacitors. The delay will vary from part to part by approxi-

mately ±15% due to process variations.

In addition, the choice of external FLT2 and FLT3 values, as well

as load on the VNEV pin will increase the delay. In this case, the

delay variation will be dominated by the part-to-part tolerance of the

external capacitors.

RMS CIRCUIT DESCRIPTION

The rms processing is done using a proprietary translinear tech-

nique. This method is a mathematically accurate rms computing

approach and achieves unprecedented rms accuracies for complex

modulation signals irrespective of the crest factor of the input

signal. An integrating filter capacitor does the square-domain aver-

aging. The VRMS output can be expressed as

VRMS=A× T1

2VIN2×dt

2−T1

(1)

Note that A is a scaling parameter that is decided on by the on-chip

resistor ratio, and there are no other scaling parameters involved in

this computation, which means that the rms output is inherently free

from any sources of error due to temperature, supply, and process

variation.

RMS FILTERING

The on-chip rms filtering corner is internally set by a 400 Ω resistor

and a 20 pF capacitor, yielding a corner frequency of approximately

20 MHz. Whereas this filters out all carrier frequencies, most of

the modulation envelope is not filtered. For adequate rms filtering,

connect an external filter capacitor between FLT4 (Pin 14) and

VPOS (Pin 15). This capacitance acts on the internal 400 Ω resistor

(see Figure 48) to yield a new corner frequency for the rms filter

given by

CFLT4= 1

2π×fRMS×400 Ω

−20 pF

(2)

For example, a supply-referenced 0.1 µF capacitor on FLT4 re-

duces the corner frequency of the rms averaging circuit to approxi-

mately 4 kHz.

RMS filtering has a direct impact on rms accuracy. For most

accurate detection, the rms filter corner should be low enough to

filter out most of the modulation content. This will correspond to a

corner frequency that is significantly lower than the bandwidth of

the signal being measured. See the Choosing a Value for the RMS

Averaging Capacitor (CFLT4) section for more details and filtering

options.

OUTPUT DRIVE CAPABILITY AND BUFFERING

The envelope output of the ADL5511 is presented on the VENV

pin as a single-ended buffered output with low output impedance.

To achieve high envelope bandwidth, this output is not ground

referenced, unlike the VRMS output, which is ground referenced.

The VENV output has a no signal dc value of about 1.1 V. This

dc reference is temperature dependent and is presented as a

standalone reference voltage on the EREF pin and as a buffered

output. The true envelope at any instant of time is simply (VENV −

VEREF), but these two pins do not constitute a differential output.

EREF is a fixed dc voltage and VENV carries all the envelope

information.

The VENV output is capable of supporting a parallel load of 500 Ω

and 10 pF at full-scale envelope output and maximum bandwidth.

Lighter loads (higher R and lower C) are always recommended

whenever possible to minimize power consumption and achieve

maximum possible bandwidth. The maximum source/ sink current

capacity of the VNEV output is 15 mA peak and load conditions

should be such that this is not exceeded. The maximum output

voltage at this pin is approximately (VPOS − 1.5) V.

For the case of ac coupling only, the VENV output can drive a 50

Ω load, as long as the maximum signal swing does not exceed

an amplitude of approximately 1.5 V p-p. This corresponds to the

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