ADL5511ACPZ-R7 datasheet(18/26 Pages) AD

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Data Sheet

ADL5511

CIRCUIT DESCRIPTION

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Rev. E | 18 of 26

peak signal current of 15 mA into the 50 Ω load. If a 50 Ω drive

capability is desired, the maximum input signal to ADL5511 should

be adjusted, such that this output swing condition is not exceeded.

A 50 Ω load should never be dc coupled to the VENV output, as

it presents a current draw of >20 mA even for no-signal condition

corresponding to 1.1 V nominal dc voltage at the VENV pin.

The VRMS buffered output can source a maximum current of 3

mA, but is not designed to sink any appreciable amount of current.

If current sink capability is desired at this pin, a shunt resistance

to ground can be connected. The VRMS output has an on-chip

series resistance of 100 Ω, to allow a low-pass filtering of the

residual ripple using a single shunt capacitor at this pin. Large

shunt capacitors at this pin may also require a shunt resistor to

be placed to allow fast discharging of the capacitor. The internal

shunt resistance on the VRMS pin is 10 kΩ. Note that any shunt

resistance placed on this pin creates a resistive divider with the

on-chip 100 Ω series resistance.

The EREF output buffer also has 3 mA current sourcing capability.

The internal shunt resistance on this pin through which any current

must be sunk, is 12 kΩ. A capacitor to ground can be placed on this

pin to eliminate any RF or envelope ripple at this pin to ensure that

voltage at this pin acts as a clean reference for the VENV output for

all possible carrier and envelope frequencies.

Viewing the Envelope on an Oscilloscope

When viewing the VENV output on an oscilloscope, use a low

capacitive FET probe. This reduces the capacitance presented to

the VENV output and avoids the corresponding effects of larger

capacitive loads.

ADL5511ACPZ-R7 数据表(PDF) 18 Page - Analog Devices