PPC440SPE-RNB533C datasheet(15/80 Pages) AMCC

15 / 80 page

PowerPC 440SPe Embedded Processor

Revision 1.23 - Sept 21, 2006

AMCC Proprietary

Preliminary Data Sheet

General Purpose Timers (GPT)

Provides a time base counter and system timers additional to those defined in the processor core.

• 32-bit time base counter driven by the OPB bus clock

• Seven 32-bit compare timers

General Purpose IO (GPIO) Controller

• Controller functions and GPIO registers are programmed and accessed by means of memory-mapped OPB

bus master accesses.

• The 32 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO

capabilities acts as a GPIO or is used for another purpose.

• Each GPIO output is a separately programmable tri-state driver (pull-up, pull-down, or open-drain).

Universal Interrupt Controller (UIC)

Four cascaded Universal Interrupt Controllers (UIC) process internal on-chip and external processor interrupts.

Note: Processor specific interrupts (for example, page faults) do not use UIC resources.

Features include:

• 16 external interrupts

• 101 internal interrupts

• Edge-triggered or level-sensitive

• Positive- or negative-active

• Non-critical or critical interrupt to the on-chip processor core

• Programmable interrupt priority ordering

• Programmable critical interrupt vector for faster vector processing

JTAG

Features include:

• IEEE 1149.1 Test Access Port

• IBM RISCWatch Debugger support

• JTAG Boundary Scan Description Language (BSDL)

PPC440SPE-RNB533C 数据表(PDF) 15 Page - Applied Micro Circuits Corporation