PPC440SPE-RNB533C datasheet(57/80 Pages) AMCC

57 / 80 page

PowerPC 440SPe Embedded Processor

Revision 1.23 - Sept 21, 2006

AMCC Proprietary

Preliminary Data Sheet

SYSPLLG

Ground for the SYS_PLL

n/a

SYSPLLV

Analog 1.5V Filtered Supply voltages input for the

SYS_PLL

A separate filter for all analog voltages is recommended.

In/a

SYS2PLLG

Ground for the DDR_PLL (SDRAM)

n/a

SYS2PLLV

Analog 1.5V Filtered Supply voltages input for the

DDR_PLL (SDRAM)

A separate filter for all analog voltages is recommended.

In/a

GND

Logic and I/O voltage ground.

n/a

OVDD

3.3V I/O supply (except DDR SDRAM and PCI-X).

n/a

PxVDD

PCI-X I/O voltage supply.

3.3 V for PCI and PCI-X

1.5 V for PCI-X 266 DDR Mode 2

n/a

SVDD

DDR SDRAM I/O voltage supply.

2.5V for DDR1 SDRAM

1.8V for DDR2 SDRAM

n/a

VDD

1.5V Logic voltage supply.

n/a

Miscellaneous

PSRO1

Performance Screen Ring Oscillator.

n/a

THERMALDA

THERMALDB

On chip Diode for thermal monitoring.

P diffusion on Pad A (In), and N on pad B (out)

Reserved

Do not connect voltage, ground, or any signals to these

pins.

n/a

Table 6. Signal Functional Description (Sheet 8 of 8)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3k

Ω to 3.3V)

3. Must pull down (recommended value is 1k

Ω)

4. If not used, must pull up (recommended value is 3k

Ω to 3.3V)

5. If not used, must pull down (recommended value is 1k

Ω)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

PPC440SPE-RNB533C 数据表(PDF) 57 Page - Applied Micro Circuits Corporation

PPC440SPE-RNB533C 数据表(HTML) 57 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表下载