PPC440SPE-RNB533C datasheet(50/80 Pages) AMCC

50 / 80 page

PowerPC 440SPe Embedded Processor

AMCC Proprietary

Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

Table 6. Signal Functional Description (Sheet 1 of 8)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3k

Ω to 3.3V)

3. Must pull down (recommended value is 1k

Ω)

4. If not used, must pull up (recommended value is 3k

Ω to 3.3V)

5. If not used, must pull down (recommended value is 1k

Ω)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

PCI-Express 0:2 Interfaces

PCIE_REFCLK

PCI Express Reference Clock: 100 MHz differential

clock pair. Input type is controlled by bit 3 of the

PESDR0_PLLLCT1[MCENT] register.

0 2.5V CMOS or LVDS

1 2.5V LVPECL (recommended)

Diff PECL

PCIE0Tx[7:0]

PCIE1:2Tx[3:0]

PCI Express Serial Data Transmit differential signals

LSB is 0.

X8 Mode: All PCIE0Tx[7:0]/PCIE0Tx[7:0] are used.

X4 Mode: Only PCIE0Tx[3:0]/PCIE0Tx[3:0] are used.

Diff PECL

PCIE0Rx[7:0]

PCIE1:2Rx[3:0]

PCI Express Serial Data Receive differential signals

LSB is 0.

X8 Mode: All PCIE0Rx[7:0]/PCIE0Rx[7:0] are used.

X4 Mode: Only PCIE0Rx[3:0]/PCIE0Rx[3:0] are used

Diff PECL

PCIE0:2AVREG

PCI Express Analog Observation point for internal

voltage regulator

PCIECalRP

PCIECalRN

Positive and negative inputs for a 1 Kohm ±1% PCI

Express External calibration resistor

PCIEPLLTSTON

Enable PCI Express PLL test modes.

PCI-X0 Interfaces

PCIX0Ack64/PCIX0ECC1

Ack64 or ECC1.

Normally used as Ack64 indicating that the target can

transfer data using 64 bits.

Used as ECC1 for PCIX mode 2.

I/O

3.3V PCI or

1.5V PCI for

mode 2

PCIX0AD63:00

Address/Data bus (bidirectional) for PCI-X0

I/O

3.3V PCI or

1.5V PCI for

mode 2

PCIX0BE7:0

PCI-X Byte Enables for PCI-X0

I/O

3.3V PCI or

1.5V PCI for

mode 2

PCIX0CalG0

PCIX0CalR0

Balls G and R for a 114 Ohm External calibration

resistor. Used to control PCI-X I/O Impedance at 57

Ohm.

INA

PCIX0Cap

Capable of PCI-X operation.

This analog input is sampled to configure PCI and

determine the state of the PCIX0VC output signal:

0.00VDD (0.0V) = Conventional PCI & PCIX0VC = 0

0.49VDD (1.0V) = PCI-X DDR 266 Mode 2 &

PCIX0VC = 1

0.75VDD (2.5V) = PCI-X 66 & PCIX0VC = 0

1.00VDD (3.3V) = PCI-X 133 & PCIX0VC = 0

INA

PPC440SPE-RNB533C 数据表(PDF) 50 Page - Applied Micro Circuits Corporation

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PPC440SPE-RNB533C 数据表(PDF) 50 Page - Applied Micro Circuits Corporation

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