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PPC440SP-RNC667C 数据表(PDF) 73 Page - Applied Micro Circuits Corporation

部件名 PPC440SP-RNC667C
功能描述  PowerPC 440SP Embedded Processor
PDF  85 Pages
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制造商  AMCC [Applied Micro Circuits Corporation]
网页  http://www.amcc.com
标志 AMCC - Applied Micro Circuits Corporation

PPC440SP-RNC667C 数据表(HTML) 73 Page - Applied Micro Circuits Corporation

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PowerPC 440SP Embedded Processor
Revision 1.23 - Sept 26, 2006
AMCC Proprietary
73
Data Sheet
Ethernet Interface
EMCCD
na
na
19.1
8.7
1, async
EMCCrS
na
na
19.1
8.7
1, async
EMCMDClk
na
na
na
na
19.1
8.7
1, async
EMCMDIO
19.1
8.7
EMCMDClk
EMCRxD0:7
4
1
na
na
19.1
8.7
EMCRxClk
EMCRxDV
4
1
na
na
19.1
8.7
EMCRxClk
EMCRxErr
na
na
19.1
8.7
EMCRxClk
EMCRxClk
na
na
19.1
8.7
1, async
EMCRefClk
na
na
19.1
8.7
EMCTxClk
na
na
na
na
19.1
8.7
1, async
EMCGTxClk
na
na
na
na
19.1
8.7
1, async
EMCTxD0:7
na
na
15
2
19.1
8.7
EMCTxClk
EMCTxEn
na
na
15
2
19.1
8.7
EMCTxClk
EMCTxErr,
na
na
15
2
19.1
8.7
EMCTxClk
Internal Peripheral Interface
IIC0SClk
na
na
na
na
15.3
10.2
IIC0SDA
15.3
10.2
IIC0SClk
IIC1SClk
na
na
na
na
15.3
10.2
IIC1SDA
15.3
10.2
IIC0SClk
UARTSerClk
na
na
na
na
19.1
8.7
UART0_Rx
na
na
UARTSerClk
UART0_Tx
na
na
19.1
8.7
UARTSerClk
UART0_DCD
na
na
19.1
8.7
async
UART0_DSR
na
na
19.1
8.7
async
UART0_CTS
na
na
19.1
8.7
async
UART0_DTR
na
na
19.1
8.7
async
UART0_RI
na
na
async
UART0_RTS
na
na
19.1
8.7
async
UART1_Rx
na
na
19.1
8.7
UARTSerClk
UART1_Tx
na
na
19.1
8.7
UARTSerClk
UART1_DSR/CTS
na
na
19.1
8.7
async
UART1_RTS/DTR
na
na
19.1
8.7
async
UART2_Rx
na
na
19.1
8.7
UARTSerClk
UART2_Tx
na
na
19.1
8.7
UARTSerClk
Interrupts Interface
IRQ0:5
na
na
async
JTAG Interface
TDI
n/a
n/a
n/a
n/a
async
TMS
n/a
n/a
n/a
n/a
async
TDO
n/a
n/a
19.1
8.7
async
TCK
n/a
n/a
n/a
n/a
async
TRST
n/a
n/a
n/a
n/a
async
Table 14. I/O Specifications—All Speeds
(Sheet 2 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133.33MHz. PCI-X input setup time requirement is 1.2ns for 133.33MHz
and 1.7ns for 66.66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66.66MHz. PCI output hold time
requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.
3. These are DDR signals that can change on both the positive and negative clock transitions.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)



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