PPC405GPR-3JB266Z datasheet(11/57 Pages) AMCC

11 / 57 page

405GPr – Power PC 405GPr Embedded Processor

AMCC

Revision 2.04 – September 7, 2007

Data Sheet

- Programmable CSon, CSoff relative to address

- Programmable OEon, WEon, WEoff (0 to 3 clock cycles) relative to CS

• Programmable address mapping

• Peripheral Device pacing with external “Ready”

• External master interface

- Write posting from external master

- Read prefetching on PLB for external master reads

- Bursting capable from external master

- Allows external master access to all non-EBC PLB slaves

- External master can control EBC slaves for own access and control

DMA Controller

• Supports the following transfers:

- Memory-to-memory transfers

- Buffered peripheral to memory transfers

- Buffered memory to peripheral transfers

• Four channels

• Scatter/gather capability for programming multiple DMA operations

• 8-, 16-, 32-bit peripheral support (OPB and external)

• 32-bit addressing

• Address increment or decrement

• Internal 32-byte data buffering capability

• Supports internal and external peripherals

• Support for memory mapped peripherals

• Support for peripherals running on slower frequency buses

PPC405GPR-3JB266Z 数据表(PDF) 11 Page - Applied Micro Circuits Corporation