PPC405GPR-3JB266Z datasheet(33/57 Pages) AMCC

33 / 57 page

405GPr – Power PC 405GPr Embedded Processor

AMCC

Revision 2.04 – September 7, 2007

Data Sheet

PerCS0

Peripheral chip select bank 0.

5V tolerant

3.3V LVTTL

PerCS1:7[GPIO10:16]

Seven additional peripheral chip selects

General Purpose I/O. To access this function, software must toggle a

DCR bit.

O[I/O]

5V tolerant

3.3V LVTTL

1, 7

PerOE

Used by either the peripheral controller or the DMA controller

depending upon the type of transfer involved. When the PPC405GPr

is the bus master, it enables the selected device to drive the bus.

5V tolerant

3.3V LVTTL

PerR/W

Used by the PPC405GPr when not in external master mode, as

output by either the peripheral controller or DMA controller depending

upon the type of transfer involved. High indicates a read from

memory, low indicates a write to memory.

Otherwise it used by the external master as an input to indicate the

direction of data transfer.

I/O

5V tolerant

3.3V LVTTL

PerReady

Used by a peripheral slave to indicate it is ready to transfer data.

5V tolerant

3.3V LVTTL

PerBLast

Used by the PPC405GPr when not in external master mode,

otherwise used by external master. Indicates the last transfer of a

memory access.

I/O

5V tolerant

3.3V LVTTL

1, 7

DMAReq0:3

DMAReq0:3 are used by slave peripherals to indicate they are

prepared to transfer data.

5V tolerant

3.3V LVTTL

DMAAck0:3

DMAAck0:3 are used by the PPC405GPr to cause the DMA

peripheral to transfer data.

5V tolerant

3.3V LVTTL

EOT0:3/TC0:3

End Of Transfer/Terminal Count.

I/O

5V tolerant

3.3V LVTTL

Signal Functional Description (Sheet 4 of 8)

Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.

3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

7. Pull-up may be required. See “External Bus Control Signals” on page 29.

Signal Name

Description

I/O

Type

Notes

PPC405GPR-3JB266Z 数据表(PDF) 33 Page - Applied Micro Circuits Corporation

PPC405GPR-3JB266Z 数据表(HTML) 33 Page - Applied Micro Circuits Corporation

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PPC405GPR-3JB266Z 数据表(PDF) 33 Page - Applied Micro Circuits Corporation

PPC405GPR-3JB266Z 数据表(HTML) 33 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

数据表 下载

链接网址

数据表下载