405GPr – Power PC 405GPr Embedded Processor

52

AMCC

Revision 2.04 – September 7, 2007

Data Sheet

L25

EMCTxD1

J26

EMCTxD0

Divide by 1

0

0

Divide by 2

0

1

Divide by 3

1

0

Divide by 4

1

1

D18

GPIO1[TS1E]

C20

GPIO2[TS2E]

Divide by 1

0

0

Divide by 2

0

1

Divide by 3

1

0

Divide by 4

1

1

K25

EMCTxErr

K23

EMCTxEn

Divide by 2

0

0

Divide by 3

0

1

Divide by 4

1

0

Divide by 5

1

1

ROM Width

AC2

UART1_Tx

AD2

UART1_RTS/

UART1_DTR

8-bit ROM

0

0

16-bit ROM

0

1

32-bit ROM

1

0

Reserved

1

1

ROM Location

U2

HoldAck

PPC405GPr Peripheral Attach

0

PPC405GPr PCI Attach

1

PCI Asynchronous Mode Enable

Y3

ExtAck

Synchronous PCI Mode

0

Asynchronous Mode

1

AF18

GPIO4[TS2O]

Internal Arbiter Disabled

0

Internal Arbiter Enabled

1

Note:

1. The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the

PPC405GPr. These bits are shown for information only; and do not require modification except in special clocking circumstances such as

spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405GPr, visit the technical

documents area of the AMCC PowerPC web site.

2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in “Clocking

Specifications” on page 43. Further requirements are detailed in the Clocking chapter of the PowerPC 405GPr Embedded Processor

User’s Manual.

3. Additional consideration must be given to pins that normally function as Trace signals. Improved design margin can be gained by using

three-state buffers instead of strapping resistors, and minimizing trace lengths and stubs.

Function

Option

Ball Strapping