HT48RA3 datasheet(11/38 Pages) HOLTEK

11 / 38 page

HT48RA3/HT48CA3

Rev. 1.30

October 12, 2007

Watchdog Timer

- WDT

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator), instruction clock (system

clock divided by 4), determines the ROM code option.

This timer is designed to prevent a software malfunction

or sequence from jumping to an unknown location with

unpredictable results. The Watchdog Timer can be dis-

abled by ROM code option. If the Watchdog Timer is dis-

abled, all the executions related to the WDT result in no

operation.

Once the internal WDT oscillator (RC oscillator with a

period of 90

ms at 3V normally) is selected, it is first di-

vided by 256 (8-stage) to get the nominal time-out pe-

riod of 23ms at 3V. This time-out period may vary with

temperatures, VDD and process variations. By invoking

the WDT prescaler, longer time-out periods can be real-

ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the

WDTS) can give different time-out periods. If WS2,

WS1, and WS0 are all equal to 1, the division ratio is up

to 1:128, and the maximum time-out period is 2.9s/3V

seconds. If the WDT oscillator is disabled, the WDT

clock may still come from the instruction clock and oper-

ates in the same manner except that in the HALT state

the WDT may stop counting and lose its protecting pur-

pose. In this situation the logic can only be restarted by

external logic. The high nibble and bit 3 of the WDTS are

reserved for user

¢s defined flags, which can be used to

indicate some specified status.

If the device operates in a noisy environment, using the

on-chip RC oscillator (WDT OSC) is strongly recom-

mended, since the HALT will stop the system clock.

WS2

WS1

WS0

Division Ratio

000

1:1

001

1:2

010

1:4

011

1:8

1:16

1:32

1:64

1:128

WDTS Register

The WDT overflow under normal operation will initialize

²chip reset² and set the status bit ²TO². But in the HALT

mode, the overflow will initialize a

²warm reset² and only

the program counter and SP are reset to zero. To clear

the contents of WDT (including the WDT prescaler),

three methods are adopted; external reset (a low level to

RES), software instruction and a

²HALT² instruction.

The software instruction include

²CLR WDT² and the

other set

-²CLR WDT1² and ²CLR WDT2². Of these

two types of instruction, only one can be active depend-

ing on the ROM code option

-²CLR WDT times selec-

tion option

².Ifthe ²CLR WDT² is selected (i.e. CLRWDT

times equal one), any execution of the

²CLR WDT² in-

struction will clear the WDT. In the case that

²CLR

WDT1

² and ²CLR WDT2² are chosen (i.e. CLRWDT

times equal two), these two instructions must be exe-

cuted to clear the WDT; otherwise, the WDT may reset

the chip as a result of time-out.

Power Down Operation

- HALT

The HALT mode is initialized by the

²HALT² instruction

and results in the following...

· The system oscillator will be turned off but the WDT

oscillator remains running (if the WDT oscillator is se-

lected).

· The contents of the on chip RAM and registers remain

unchanged.

· WDT and WDT prescaler will be cleared and re-

counted again (if the WDT clock is from the WDT os-

cillator).

· All of the I/O ports maintain their original status.

· The PDF flag is set and the TO flag is cleared.

The system can leave the HALT mode by means of an

external reset, an interrupt, an external falling edge sig-

nal on port A or a WDT overflow. An external reset

causes a device initialization and the WDT overflow per-

forms a

²warm reset². After the TO and PDF flags are

examined, the reason for chip reset can be determined.

The PDF flag is cleared by system power-up or execut-

ing the

²CLR WDT² instruction and is set when execut-

ing the

²HALT² instruction. The TO flag is set if the WDT

time-out occurs, and causes a wake-up that only resets

the program counter and SP; the others remain in their

original status.

S y s t e m C l o c k / 4

8 - b i t C o u n t e r

W D T P r e s c a l e r

7 - b i t C o u n t e r

8 - t o - 1 M U X

W D T T i m e - o u t

W S 0 ~ W S 2

R O M

C o d e

O p t i o n

S e l e c t

W D T

O S C

Watchdog Timer

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