HT48RA3 datasheet(14/38 Pages) HOLTEK

14 / 38 page

HT48RA3/HT48CA3

Rev. 1.30

October 12, 2007

Timer/Event Counter

Two timer/event counters are (TMR0, TMR1) imple-

mented in the device. The Timer/Event Counter 0 con-

tains an 8-bit programmable count-up counter and the

clock may come from an external source or the system

clock. The Timer/Event Counter 1 contains an 16-bit

programmable count-up counter and the clock may

come from an external source or the system clock di-

vided by 4.

Of the two timer/event counters, using external clock in-

put allows the user to count external events, measure

time internals or pulse widths, or generate an accurate

time base. While using the internal clock allows the user

to generate an accurate time base.

Only the Timer/Event Counter 0 can generate PFD sig-

nal by using external or internal clock, and PFD fre-

quency is determine by the equation fINT/[2

´(256-N)].

There are 2 registers related to Timer/Event Counter 0;

TMR0(0DH), TMR0C(0EH). In Timer/Event Counter 0

counting mode (T0ON=1), writing TMR0 will only put the

written data to preload register (8 bits). The Timer/Event

Counter 0 preload register is changed by each writing

TMR0 operations. Reading TMR0 will also latch the

TMR0 to the destination. The TMR0C is the Timer/Event

Counter 0 control register, which defines the operating

mode, counting enable or disable and active edge.

The T0M0, T0M1 bits define the operating mode. The

event count mode is used to count external events,

which means the clock source comes from an external

(TMR0) pin. The timer mode functions as a normal timer

with the clock source coming from the fINT clock. The

pulse width measurement mode can be used to count

the high or low level duration of the external signal

(TMR0). The counting is based on the fINT clock.

In the event count or timer mode, once the Timer/Event

Counter 0 starts counting, it will count from the current

contents in the Timer/Event Counter 0 to FFH. Once

overflow occurs, the counter is reloaded from the

Timer/Event Counter 0 preload register and generates

the corresponding interrupt request flag (T0F; bit 5 of

INTC) at the same time.

In pulse width measurement mode with the T0ON and

T0E bits are equal to one, once the TMR0 has received

a transition from low to high (or high to low if the T0E bit

is 0) it will start counting until the TMR0 returns to the

original level and reset the T0ON. The measured result

will remain in the Timer/Event Counter 0 even if the acti-

vated transition occurs again. In other words, only one

cycle measurement can be done. Until setting the

T0ON, the cycle measurement will function again as

long as it receives further transition pulse. Note that, in

this operating mode, the Timer/Event Counter 0 starts

counting not according to the logic level but according to

the transition edges. In the case of counter overflows,

the counter 0 is reloaded from the Timer/Event Counter

0 preload register and issues the interrupt request just

like the other two modes.

To enable the counting operation, the timer ON bit

(T0ON; bit 4 of TMR0C) should be set to 1. In the pulse

width measurement mode, the T0ON will be cleared au-

tomatically after the measurement cycle is complete.

But in the other two modes the T0ON can only be reset

by instructions. The overflow of the Timer/Event Coun-

ter 0 is one of the wake-up sources. No matter what the

operation mode is, writinga0to ET0I can disabled the

corresponding interrupt service.

In the case of Timer/Event Counter 0 OFF condition,

writing data to the Timer/Event Counter 0 preload regis-

ter will also load the data to Timer/Event Counter 0. But

if the Timer/Event Counter 0 is turned on, data written to

the Timer/Event Counter 0 will only be kept in the

Timer/Event Counter 0 preload register. The

Timer/Event Counter 0 will still operate until the overflow

occurs (a Timer/Event Counter 0 reloading will occur at

the same time).

When the Timer/Event Counter 0 (reading TMR0) is

read, the clock will be blocked to avoid errors. As this

may results in a counting error, this must be taken into

consideration by the programmer.

The bit 0~2 of the TMR0C can be used to define the

pre-scaling stages of the internal clock sources of

Timer/Event Counter 0. The definitions are as shown.

Bit

No.

Label

Function

0~2

T0PSC0~

T0PSC2

To define the prescaler stages,

T0PSC2, T0PSC1, T0PSC0=

000: fINT=fSYS/2

001: fINT=fSYS/4

010: fINT=fSYS/8

011: fINT=fSYS/16

100: fINT=fSYS/32

101: fINT=fSYS/64

110: fINT=fSYS/128

111: fINT=fSYS/256

T0E

To define the TMR0 active edge of

Timer/Event Counter 0

(0=active on low to high;

1=active on high to low)

T0ON

To enable/disable timer 0 counting

(0=disabled; 1=enabled)

Unused bit, read as

²0²

T0M0

T0M1

To define the operating mode

(T0M1, T0M0)

01=Event count mode

(external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

TMR0C (0EH) Register

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