HT48RA3 datasheet(16/38 Pages) HOLTEK

16 / 38 page

HT48RA3/HT48CA3

Rev. 1.30

October 12, 2007

Timer/Event Counter 1 preload register. The

Timer/Event Counter 1 will still operate until the overflow

occurs (a Timer/Event Counter 1 reloading will occur at

the same time).

When the Timer/Event Counter 1 (reading TMR1H) is

read, the clock will be blocked to avoid errors. As this

may results in a counting error, this must be taken into

consideration by the programmer.

The definitions of the TMR1C are as shown.

Bit No.

Label

Function

0~2

Unused bit, read as

²0²

T1E

To define the active edge of TMR1 pin

input signal

(0/1: active on low to high/high to low)

T1ON

To enable/disable timer 1 counting

(0/1: disabled/enabled)

Unused bit, read as

²0²

T1M0

T1M1

To define the operating mode

(T1M1, T1M0)

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

TMR1C (11H) Register

Input/Output Ports

There are 23 bi-directional input/output lines in the mi-

cro-controller, labeled from PA to PC and PF, which are

mapped to the data memory of [12H], [14H], [16H] and

[1CH], respectively. All of these I/O ports can be used as

input and output operations. For input operation, these

ports are non-latching, that is, the inputs must be ready

at the T2 rising edge of instruction

²MOV A,[m]² (m =

12H, 14H, 16H or 1CH). For output operation, all the

data is latched and remains unchanged until the output

latch is rewritten.

Each I/O line has its own control register (PAC, PBC,

PCC, PFC) to control the input/output configuration.

With this control register, CMOS output or Schmitt trig-

ger input with or without (depends on options) pull-high

resistor structures can be reconfigured dynamically (i.e.,

on-the fly) under software control. To function as an in-

put, the corresponding latch of the control register has to

be set as

²1². The pull-high resistor (if the pull-high re-

sistor is enabled) will be exhibited automatically. The in-

put sources also depends on the control register. If the

control register bit is

²1², the input will read the pad state

(

²mov² and read-modify-write instructions). If the control

internal data bus (

²mov² and read-modify-write instruc-

tions). The input paths (pad state or latches) of

read-modify-write instructions are dependent on the

control register bits. For output function, CMOS is the

only configuration. These control registers are mapped

to locations 13H, 15H, 17H and 1DH.

After a chip reset, these input/output lines stay at high

levels (pull-high options) or floating state (non-pull-high

options). Each bit of these input/output latches can be

set or cleared by

²SET [m].i² (m=12H, 14H, 16H or 1CH)

instructions. Some instructions first input data and then

follow the output operations. For example,

²SET [m].i²,

²CLR [m].i², ²CPLA [m]² read the entire port states into

the CPU, execute the defined operations (bit-operation),

and then write the results back to the latches or the ac-

cumulator.

V D D

P A 0 ~ P A 7

P B 0 / P F D

P B 1 ~ P B 7

P C 0 ~ P C 5

P F 0

P F D E N

( P B 0 O n l y )

O P 0 ~ O P 7

I N T f o r P F 0 O n l y

S y s t e m W a k e - u p

( P A o n l y )

R e a d D a t a R e g i s t e r

P B 0

P F D

( P B 0 O n l y )

C K Q B

C o n t r o l B i t

P U

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

P F D f o r P B 0 o n l y , c o n t r o l = P B 0 d a t a r e g i s t e r

Input/Output Ports

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