HT48RA3/HT48CA3

Rev. 1.30

17

October 12, 2007

Each line of port A has the capability of waking-up the

device. The highest 2 bits of port C and 7 bits of port F

are not physically implemented; on reading them a

²0² is

returned whereas writing then results in a no-operation.

Pull-high resistors of each port are decided by an option

bit.

The PB0 is pin-shared with PFD signal, respectively. If

the PFD option is selected, the output signal in output

mode of PB0 will be the PFD signal. The input mode al-

ways remain its original functions. The PF0 and PC0 are

pin-shared with INT and TMR 0. The INT signal is di-

rectly connected to PF0. The PFD output signal (in out-

put mode) are controlled by the PB0 data register only.

The truth table of PB0/PFD is listed below.

The truth table of PB0/PFD is as shown.

PBC (15H) Bit0

I

O

O

O

PB0/PFD Option

x

PB0

PFD

PFD

PB0 (14H) Bit0

x

D

0

1

PB0 Pad Status

I

D

0

PFD

Note:

I: Input; O: Output; D: Data

Bank Pointer

There is a bank pointer used to control the program flow

to go to any banks. A bank contains 8K

´16 address

space. The contents of bank pointer are load into pro-

gram counter when the JMP or CALL instruction is exe-

cuted. The program counter is a 15-bit register whose

contents are used to specify the executed instruction

addresses.

When calling a subroutine or an interrupt event occur-

ring, the contents of the program counter are save into

stack registers. If a returning from subroutine occurs,

the contents of the program counter will restore from

stack registers.

Low Voltage Reset

- LVR

The microcontroller provides low voltage reset circuit in

order to monitor the supply voltage of the device. If the

supply voltage of the device is within the range

tomatically reset the device internally.

The LVR includes the following specifications:

original state to exceed 1ms. If the low voltage state

does not exceed 1ms, the LVR will ignore it and do not

perform a reset function.

²OR² function with the external

RES signal to perform chip reset.

5 . 5 V

1 . 8 V

0 . 9 V

5 . 5 V

0 . 9 V

0 V

R e s e t S i g n a l

R e s e t

* 1

* 2

N o r m a l O p e r a t i o n

R e s e t

L V R D e t e c t V o l t a g e

Low Voltage Reset

Note:

²*1² To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system

clock pulses before entering the normal operation.

²*2² Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters

the reset mode.