GL646USB datasheet(10/44 Pages) GENESYS

10 / 44 page

GL646USB

Rev. 1.4

-9-

H_BUSY(DMA_ACK)

EPP nWait or DMA Acknowledge

H_ACK(IO_RD)

EPP Intr or DMA IO Read

H_PE(IO_WR)

EPP AckDataReq or DMA IO Write

H_ERR(DMA_DRQ)

EPP nDataAvail or DMA Data Request

HD0~HD7

EPP Data Bus or MPU Data Bus

DMAD0~7

DMA Data Bus

Support IO Ports

GPIO1~12

General Purpose Input Output

MT_PH0~5

Bi-polar : MT_PH5=PHASE1

MT_PH4=PHASE2

MT_PH3=I11

MT_PH2=I01

MT_PH1=I12

MT_PH0=I02

Uni-polar : MT_PH3=PHASE A

MT_PH2=PHASE B

MT_PH1=PHASE /A

MT_PH0=PHASE /B

HOME

Sense carriage home position

USB Interface

VMO

D+

VPO

D-

VCP

3.3V

CCD/CIS Control Signals

CCD_CK1X

CCD Shift register clock1 or CIS clock output

CCD_CK2X

CCD Shift register clock2 or CIS clock output

CCD_CPX

CCD Clamp gate clock or CIS clock output

CCD_RSX

CCD Reset gate clock or CIS clock output

CCD_TGX

CCD Transfer gate clock for R channel or CIS Line start pulse

CCD_TGG

CCD Transfer gate clock for G channel

CCD_TGB

CCD Transfer gate clock for B channel

RGBSEL0

RGB channel selection pin or CCD Shift register clock3

XPA_SW

Transparency lamp power control or CIS Green LED array control

LAMP_SW

Flatbed lamp power control or CIS Red LED array control

LED_B

CIS Blue LED array control

FRONT-END

R_IN

Red channel input signal

G_IN

Green channel input signal

B_IN

Blue channel input signal

VRLC

Selectable analog output voltage for RLC

VMID

ADC reference voltage. Derived from VRU. Normally is 2.5V

VRT

ADC reference voltage. Derived from VRU. Normally is 3.3V

VRB

ADC reference voltage. Derived from VRU. Normally is 1.7V

VRU

ADC reference voltage. Normally connected to 5V analog supply

OP0~OP7

ADC digital data output

VSMP(CDSCLK2)

Wolfson type : Video sample synchronization pulse.

GL646USB 数据表(PDF) 10 Page - GENESYS LOGIC

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