GL646USB datasheet(11/44 Pages) GENESYS

11 / 44 page

GL646USB

Rev. 1.4

-10-

This signal is applied synchronously with MCLK to specify the point of time that

the input is sampled.

Analog Device type : CDS image sampling clock

BSMP(CDSCLK1)

Analog Device type : Black level sampling clock

SCLK

Serial interface clock output for Front-end

SENLOAD

Serial interface data latch-in signal for Front-end

MCLK(ADCCLK)

Wolfson type : Master clock.

This clock is applied at either six or three times the input pixel rate depending on

the operational mode.

Analog Device type: ADC Converter sampling clock

SDI

Serial interface data output signal for Front-end

SDO

Serial interface data input signal for Front-end

DRAM

DBUS0~15

DRAM data bus

ABUS0~8

DRAM address bus

RASX

DRAM RAS signal of first memory chip

CASX

DRAM CAS signal of first memory chip

NOEX

DRAM OE(output enable) signal of first memory chip

NWEX

DRAM WE signal of first memory chip

RASY

DRAM RAS signal of second memory chip

CASY

DRAM CAS signal of second memory chip

NOEY

DRAM OE(output enable) signal of second memory chip

NWEY

DRAM WE signal of second memory chip

Miscellaneous

TSTMOD

TSTSEL0

TSTSEL1

MPU_SEL

Test mode selection pins :

{TSTMOD,TSTSEL0,TSTSEL1,MPU_SEL}=

0000 : mode1

0100 : mode2

0011 : mode3

0010 : mode4

0110 : mode5

100x : mode6

110x : mode7

101x : mode8

1110 : mode9

MTR_SEL

MTR_SEL=1 select Bi_polar

MTR_SEL=0 select Uni_polar

IX1

Clock input for crystal

IOX2

Clock output for crystal

CKSEL

MPUCLOE

Scanner controller clock selection

MPUCLK

Clock output

EXTRST_

Hardware reset input

POWER

AVDD

Analog power input

AVSS

Analog ground input

AGND

Analog ground input for USB1.1

DVDD

Digital power input

DGND

Digital ground input

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