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GL646USB 数据表(PDF) 29 Page - GENESYS LOGIC

部件名 GL646USB
功能描述  Three-in-one Scanner Controller for USB and 1394
PDF  44 Pages
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制造商  GENESYS [GENESYS LOGIC]
网页  http://www.genesyslogic.com
标志 GENESYS - GENESYS LOGIC

GL646USB 数据表(HTML) 29 Page - GENESYS LOGIC

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GL646USB
: reset: enable CCD TG position CP & RS signals.
CCD TG
Rev. 1.4
-28-
CCD CP/RS
7.16. Reg : 17H
(Write)
Default : 14H
B7~6:TGMODE[1:0]
: to set CCD TG mode.
00:without dummy line CCD TG type.
01:with dummy line CCD TG type.
10:reserved.
11:reserved.
B5~0:TGW[5:0]
:
to set CCD TG width.
7.17. Reg : 18H
(Write)
Defalut : 00H
B7 : CNSET
: set : TG and clock set to Canon CIS style.
: reset: TG and clock is non-Canon CIS style.
B6~5 :DCKSEL:
00 one time CCD Clocks speed for dummy line.
01 two time CCD Clocks speed for dummy line.
10 three time CCD Clocks speed for dummy line.
11 four time CCD Clocks speed for dummy line.
B4 :CKTOGGLE
: set : half cycle per pixel for CCD Clock 1/2.
: reset : one cycle per pixel
B3~2 :CKDELAY:
00 no delay
01 delay one system clock for CCD Clock 1/2.
10 delay two system clock for CCD Clock 1/2.
11 delay three system clock for CCD Clock 1/2.
B1~0 :CKSEL :
00 one time CCD Clock speed for capture image.
01 two time CCD Clock speed for capture image.
10 three time CCD Clock speed for capture image.
11 four time CCD Clock speed for capture image.
7.18. Reg : 19H
(Write)
Default : 00H
EXPDMY[7:0] : to set dummy line exposure time (unit = 256 pixels time).
7.19. Reg : 1AH,1BH
(Write)
Defalut : 00H,00H
CKH[4:0]: set CCD Clock rising edge position.
CKL[4:0]: set CCD Clock falling edge position.
7.20. Reg : 1CH
(Write)
Default : 00H
B7: CK3SEL
: to enable CCD Clock3
B6:CK3INV
: to reverse CCD Clock3
B5~B0: TGSEL[5:0]
: to set CCD TG for R,G and B output control
B0~1: control R Channel TG.
B2~3: control G Channel TG.
B4~5: control B Channel TG.
7.21. Reg : 1DH
(Write)
Defalut : 04H
B7 : CKMANUAL : to program CCD Clock1/2 by manual.



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