CDCE913 datasheet(17/23 Pages) TI

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CDCE913

CDCEL913

SCAS849A – JUNE 2007 – REVISED AUGUST 2007

Table 10. PLL1 Configuration Register (continued)

OFFSET(1)

Bit(2)

Acronym

Default(3)

DESCRIPTION

0 – down

SSC1DC

PLL1 SSC down/center selection:

1 – center

16h

0 – reset and stand-by

6:0

Pdiv2

01h

7-Bit Y2-Output-Divider Pdiv2:

1-to-127 is divider value

—

Reserved – do not write others than 0

17h

0 – reset and stand-by

6:0

Pdiv3

01h

7-Bit Y3-Output-Divider Pdiv3:

1-to-127 is divider value

18h

7:0

PLL1_0N [11:4]

004h

7:4

PLL1_0N [3:0]

19h

3:0

PLL1_0R [8:5]

000h

PLL1_0: 30-Bit Multiplier/Divider value for frequency fVCO1_0

7:3

PLL1_0R[4:0]

(for more information, see paragraph PLL Multiplier/Divider Definition).

1Ah

2:0

PLL1_0Q [5:3]

10h

7:5

PLL1_0Q [2:0]

4:2

PLL1_0P [2:0]

010b

1Bh

00 – fVCO1_0 < 125 MHz

01 – 125 MHz

≤ fVCO1_0 < 150 MHz

1:0

VCO1_0_RANGE

00b

fVCO1_0 range selection:

10 – 150 MHz

≤ fVCO1_0 < 175 MHz

11 – fVCO1_0 ≥ 175 MHz

1Ch

7:0

PLL1_1N [11:4]

004h

7:4

PLL1_1N [3:0]

1Dh

3:0

PLL1_1R [8:5]

000h

PLL1_1: 30-Bit Multiplier/Divider value for frequency fVCO1_1

1Eh

7:3

PLL1_1R[4:0]

(for more information see paragraph PLL Multiplier/Divider Definition)

2:0

PLL1_1Q [5:3]

10h

1Fh

7:5

PLL1_1Q [2:0]

4:2

PLL1_1P [2:0]

010b

00 – fVCO1_1 < 125 MHz

01 – 125 MHz

≤ fVCO1_1 < 150 MHz

1:0

VCO1_1_RANGE

00b

fVCO1_1 range selection:

10 – 150 MHz

≤ fVCO1_1 < 175 MHz

11 – fVCO1_1 ≥ 175 MHz

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