CDCE913 datasheet(18/23 Pages) TI

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PLL Multiplier/Divider Definition

OUT +

Pdiv

(1)

VCO + ƒIN

(2)

• P = 4 – int

log

[if P t 0 then P + 0]

• Q = int

CDCE913

CDCEL913

SCAS849A – JUNE 2007 – REVISED AUGUST 2007

At a given input frequency (ƒIN), the output frequency (ƒOUT) of the CDCE913/CDCEL913 can be calculated:

where

M (1 to 511) and N (1 to 4095) are the multiplier/divide values of the PLL; Pdiv (1 to 127) is the output

divider.

The target VCO frequency (ƒVCO) of each PLL can be calculated:

The PLL internally operates as fractional divider and needs the following multiplier/divider settings:

• N

• R = N′ – M × Q

where

′ = N

× 2P;

≥ M;

100 MHz < ƒVCO > 200 MHz.

Example:

for ƒIN = 27 MHz; M = 1; N = 4; Pdiv = 2;

for ƒIN = 27 MHz; M = 2; N = 11; Pdiv = 2;

→ fOUT = 54 MHz

→ fOUT = 74.25 MHz

→ fVCO = 108 MHz

→ fVCO = 148.50 MHz

→ P = 4 – int(log24) = 4 – 2 = 2

→ P = 4 – int(log25.5) = 4 – 2 = 2

→ N′’ = 4

× 22 = 16

→ N′’ = 11

× 22 = 44

→ Q = int(16) = 16

→ Q = int(22) = 22

→ R = 16 – 16 = 0

→ R = 44 – 44 = 0

The values for P, Q, R, and N’ are automatically calculated when using TI Pro-Clock™ software.

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Product Folder Link(s): CDCE913 CDCEL913

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