P912XDP512F0MFVR datasheet(400/1350 Pages) FREESCALE

部件名	P912XDP512F0MFVR

功能描述	Covers, S12XD, S12XB & S12XA Families

PDF	1350 Pages

Scroll/Zoom	100%

制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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400 / 1350 page

Chapter 9 Inter-Integrated Circuit (IICV2) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.17

400

Freescale Semiconductor

The number of clocks from the falling edge of SCL to the ﬁrst tap (Tap[1]) is deﬁned by the values shown

in the scl2tap column of Table 9-3, all subsequent tap points are separated by 2IBC5-3 as shown in the

tap2tap column in Table 9-3. The SCL Tap is used to generated the SCL period and the SDA Tap is used

to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time.

IBC7–6 deﬁnes the multiplier factor MUL. The values of MUL are shown in the Table 9-4.

Figure 9-5. SCL Divider and SDA Hold

The equation used to generate the divider values from the IBFD bits is:

SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)}

Table 9-4. Multiplier Factor

IBC7-6

MUL

RESERVED

SCL Divider

SDA Hold

SCL

SDA

SCL

START condition

STOP condition

SCL Hold(start)

SCL Hold(stop)

P912XDP512F0MFVR 数据表(PDF) 400 Page - Freescale Semiconductor, Inc