P912XDP512F0MFVR datasheet(397/1350 Pages) FREESCALE

部件名	P912XDP512F0MFVR

功能描述	Covers, S12XD, S12XB & S12XA Families

PDF	1350 Pages

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制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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397 / 1350 page

Chapter 9 Inter-Integrated Circuit (IICV2) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

397

9.2

External Signal Description

The IICV2 module has two external pins.

9.2.1

IIC_SCL — Serial Clock Line Pin

This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus speciﬁcation.

9.2.2

IIC_SDA — Serial Data Line Pin

This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus speciﬁcation.

9.3

Memory Map and Register Deﬁnition

This section provides a detailed description of all memory and registers for the IIC module.

9.3.1

Module Memory Map

The memory map for the IIC module is given below in Table 1-1. The address listed for each register is

the address offset.The total address for each register is the sum of the base address for the IIC module and

the address offset for each register.

P912XDP512F0MFVR 数据表(PDF) 397 Page - Freescale Semiconductor, Inc