P912XDP512F0MFVR datasheet(180/1350 Pages) FREESCALE

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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3)

MC9S12XDP512 Data Sheet, Rev. 2.17

180

Freescale Semiconductor

5.4

Functional Description

The ATD is structured in an analog and a digital sub-block.

5.4.1

Analog Sub-Block

The analog sub-block contains all analog electronics required to perform a single conversion. Separate

power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block.

5.4.1.1

Sample and Hold Machine

The sample and hold (S/H) machine accepts analog signals from the external surroundings and stores them

as capacitor charge on a storage node.

The sample process uses a two stage approach. During the ﬁrst stage, the sample ampliﬁer is used to

quickly charge the storage node.The second stage connects the input directly to the storage node to

complete the sample for high accuracy.

When not sampling, the sample and hold machine disables its own clocks. The analog electronics still draw

their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the

analog power consumption.

The input analog signals are unipolar and must fall within the potential range of VSSA to VDDA.

5.4.1.2

Analog Input Multiplexer

The analog input multiplexer connects one of the 8 external analog input channels to the sample and hold

machine.

5.4.1.3

Sample Buffer Ampliﬁer

The sample ampliﬁer is used to buffer the input analog signal so that the storage node can be quickly

charged to the sample potential.

5.4.1.4

Analog-to-Digital (A/D) Machine

The A/D Machine performs analog to digital conversions. The resolution is program selectable at either 8

or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the

stored analog sample potential with a series of digitally generated analog potentials. By following a binary

search algorithm, the A/D machine locates the approximating potential that is nearest to the sampled

potential.

When not converting the A/D machine disables its own clocks. The analog electronics still draws quiescent

current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power

consumption.

Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result

in a non-railed digital output codes.

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