P912XDP512F0MFVR datasheet(186/1350 Pages) FREESCALE

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Chapter 6 XGATE (S12XGATEV2)

MC9S12XDP512 Data Sheet, Rev. 2.17

186

Freescale Semiconductor

6.3

Memory Map and Register Deﬁnition

This section provides a detailed description of address space and registers used by the XGATE module.

The memory map for the XGATE module is given below in Figure 6-2.The address listed for each register

is the sum of a base address and an address offset. The base address is deﬁned at the SoC level and the

address offset is deﬁned at the module level. Reserved registers read zero. Write accesses to the reserved

registers have no effect.

6.3.1

This section consists of register descriptions in address order. Each description includes a standard register

diagram with an associated ﬁgure number. Details of register bit and ﬁeld function follow the register

diagrams, in bit order.

Name

9876543210

XGMCTL

00000000

XGE XGFRZ XGDBG XGSS

FACT

SWEIF

XGIE

XGEM

FRZM

DBGM

XGSSM

FACTM

SWEIFM

XGIEM

XGMCHID R

XGCHID[6:0]

Reserved

XGVBR

XGVBR[15:1]

= Unimplemented or Reserved

Figure 6-2. XGATE Register Summary (Sheet 1 of 3)

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