 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
STE2004S 数据表(PDF) 69 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STE2004S 数据表(HTML) 69 Page - STMicroelectronics |
|
|
69 / 79 page  STE2004S Electrical characteristics 69/79 Serial interface ( Figure 75) FSCLK Clock frequency VDD1 = 1.7V; 8 MHz TCYC Clock cycle SCLK 125 ns TPWH1 SCLK pulse width HIGH 60 ns TPWL1 SCLK pulse width LOW 60 ns TS2 CS setup time VDD1 = 1.7V 40 ns TH2 CS hold time VDD1 = 1.7V 50 ns TPWH2 CS minimum high time VDD1 = 1.7V 50 ns TS3 SD/C setup time 30 ns TH3 SD/C hold time 30 ns TS4 SDIN setup time 30 ns TH4 SDIN hold time 40 ns TS5 SDOUT access time 30 ns TH5 SDOUT disable time vs. SCLK 020 ns TH6 SDOUT disable time vs. CS 020 ns 1. 2. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated 3. Trise and Tfall (30%-70%) -10ns 4. CVLCD is the filtering capacitor on VLCD 5. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to VIL and VIH with an input voltage swing of VSS to VDD 6. Cb is the capacitive load for each bus line. Table 28. AC operation Symbol Parameter Test condition Min. Typ. Max. Unit F frame f osc 960 ---------- = |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
